View EM78815_1174950.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EM78815
8 Bit Microcontroller
Product Specification
DOC. VERSION 2.4
ELAN MICROELECTRONICS CORP.
February 2006
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation
Copyright (c) 2006 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (U.S.A.) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 4 5 6 CPU ....................................................................................................................1 Serial Transmitter/Receiver Interface..................................................................2 Current D/A .........................................................................................................2 Programmable Tone Generators.........................................................................2 CID......................................................................................................................2 Call Waiting .........................................................................................................3 External LCD controller (64x256 dot max for a pair of Master and Slave LCD Driver) ....3
2.8 Package Type .....................................................................................................3 Application................................................................................................................. 3 Pin Configuration ...................................................................................................... 4 Functional Block Diagram........................................................................................ 6 Pin Descriptions........................................................................................................ 7 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Power Pin............................................................................................................7 Clock Pin.............................................................................................................7 External LCD Device Control Pin........................................................................7 FSK, CW .............................................................................................................7 DTMF Receiver, OP............................................................................................8 Serial IO, Comparator, Current DA, Tone............................................................8 IO ........................................................................................................................8
7
6.8 Expand Program/Data ROM Interface ................................................................9 Function Description ...............................................................................................11 7.1 7.2 Operational Register .........................................................................................11 Operational Register Detail Description............................................................11
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 R0 Indirect Addressing Register........................................................................11 R1 Page 0 TCC Data Buffer..............................................................................12 R1 Page 1 Interrupt Flag 1 Real Value .............................................................12 R1 Page 2 Interrupt Flag 2 Real Value .............................................................12 R1 Page 3 UART Receiver Data Buffer ............................................................13 R2 Program Counter .........................................................................................13 R3 Status Register ............................................................................................14 R4 RAM Select for Common Registers R20~R3F, UART Control Register .....15 7.2.8.1 Page 0................................................................................................ 15 7.2.8.2 Page 1 Undefined Register................................................................ 15 7.2.9 Page 2 UART Control Register 1 ......................................................................15 7.2.10 Page 3 UART Control Register 2 ......................................................................16
Product Specification (V2.4) 02.17.2006
* iii
Contents
7.2.11 R5 Program Page Selection, CNT CLK & Scale Setting, CNT1 Data (L) .........20 7.2.11.1 Page 0 Program Page ....................................................................... 20 7.2.11.2 Page 1 Counter 1 Counter 2 CLK and Scale Setting ........................ 20 7.2.11.3 Page 2 Counter 1 Low 8-bit Data Buffer ............................................ 21 7.2.11.4 Page 3 DA Control ............................................................................. 21 7.2.12 R6 Port 6 I/O Data, Data ROM Data Buffer, CNT1 Data (H), DA Control .........22 7.2.12.1 Page 0 Port 6 I/O Data....................................................................... 22 7.2.12.2 Page 1 Data ROM Data Buffer .......................................................... 22 7.2.12.3 Page 2 Counter 1 High 8-bit Data Buffer ........................................... 22 7.2.12.4 Page 3 DA Control ............................................................................. 23 7.2.13 R7 Port 7 I/O Data, Data ROM Address, CNT2 Data, SPI Control ...................23 7.2.13.1 Page 0 Port 7 I/O Data....................................................................... 23 7.2.13.2 Page 1 Data ROM Address................................................................ 23 7.2.13.3 Page 2 Counter 2 Data Buffer............................................................ 24 7.2.13.4 Page 3 SPI Control Register.............................................................. 24 7.2.14 R8 Port 8 I/O Data, Data ROM Address, DTMF Receiver, SPI Data ................28 7.2.14.1 Page 0 Port 8 I/O Data....................................................................... 28 7.2.14.2 Page 1 Data ROM address................................................................ 28 7.2.14.3 Page 2 DTMF Receiver ..................................................................... 29 7.2.14.4 Page 3 SPI Data Buffer...................................................................... 31 7.2.15 R9 Port 9 I/O Data, Data ROM Address, Keytone Control................................31 7.2.15.1 Page 0 Port 9 I/O Data....................................................................... 31 7.2.15.2 Page 1 Data ROM Address................................................................ 32 7.2.15.3 Page 2 FSK/CW/DTMF Power Select ............................................... 32 7.2.15.4 Page 3 Keytone Control..................................................................... 32 7.2.16 RA CPU Power Saving, Main CLK Select, FSK, WDT Timer Comparator Control, Tone 1 Generator ................................................................................33 7.2.16.1 Page 0 Power Saving, Main CLK Select, FSK, WDT Timer .............. 33 7.2.16.2 Page 1 Undefined Register................................................................ 37 7.2.16.3 Page 2 Comparator Control Register ................................................ 37 7.2.16.4 Page 3 Tone 1 Control Register......................................................... 39 7.2.17 RB Port B I/O Data, Key Strobe, Tone 2 Generator ..........................................40 7.2.17.1 Page 0 Port B I/O Data ...................................................................... 40 7.2.17.2 Page 1 Undefined Register................................................................ 40 7.2.17.3 Page 2 Key Strobe Control Register.................................................. 40 7.2.17.4 Page 3 Tone 2 Control Register......................................................... 40 7.2.18 RC Port C I/O Data, Data RAM Data Buffer, Tone 2 Generator........................41 7.2.18.1 Page 0 Port C I/O Data ...................................................................... 41 7.2.18.2 Page 1 Data RAM Data Buffer 1........................................................ 41 7.2.18.3 Page 2 Key Strobe Control Register.................................................. 41 7.2.18.4 Page 3 Undefined Register:............................................................... 41
iv *
Product Specification (V2.4) 02.17.2006
Contents
7.2.19 RD Port D I/O Data, Data RAM address ...........................................................42 7.2.19.1 Page 0 Port D I/O Data, Data RAM Address ..................................... 42 7.2.19.2 Page 1 Data RAM Address 1 (Low 8 Bits)......................................... 42 7.2.19.3 Page 2 Undefined Register................................................................ 42 7.2.19.4 Page 3 Undefined Register................................................................ 42 7.2.20 RE Interrupt Flag 1, Data RAM Address 1 (H) CAS, Key Scan ........................42 7.2.20.1 Page 0 Interrupt Flag 1 ...................................................................... 42 7.2.20.2 Page 1 Data RAM Address 1(H) ........................................................ 43 7.2.20.3 Page 2 CAS Detected Flag, Keyscan................................................ 43 7.2.20.4 Page 3 UART Transmitter Data Buffer............................................... 46 7.2.21 RF Interrupt flag ................................................................................................46 7.2.21.1 Page 1 External Data ROM ............................................................... 47 7.2.21.2 Page 2 External Data ROM ............................................................... 47 7.2.21.3 Page 3 Unused .................................................................................. 47 7.2.22 R10~R3F (General Purpose Register)..............................................................47
7.3
Special Purpose Registers................................................................................47
7.3.1 7.3.2 7.3.3 A (Accumulator).................................................................................................47 CONT (Control Register)...................................................................................48 IOC5 Address Automatic Increase/Decrease Control, Data RAM Data Buffer 2 ...........49 7.3.3.1 Page 0 Address Automatic Increase/Decrease Control Register ...... 49 7.3.3.2 Page 1 Data RAM Data Buffer 2........................................................ 50 IOC6 Port 6 I/O Control, Data RAM Address (L)...............................................51 7.3.4.1 Page 0 Port 6 I/O Control................................................................... 51 7.3.4.2 Page 1 Data RAM Address 2 (L)........................................................ 51 IOC7 PORT 7 I/O Control, Data RAM Address 2 (H)........................................51 7.3.5.1 Page 0 Port 7 I/O Control................................................................... 51 7.3.5.2 Page 1 Data RAM Address 2 (H) ....................................................... 51 IOC8 Port 8 I/O Control .....................................................................................52 7.3.6.1 Page 0 Port 8 I/O Control................................................................... 52 7.3.6.2 Page 1 Undefined Register................................................................ 52 IOC9 Port 9 I/O Control .....................................................................................52 7.3.7.1 Page 0 Port 9 I/O Control................................................................... 52 7.3.7.2 Page 1 Undefined Register................................................................ 52 IOCA Undefined Register..................................................................................52
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8 7.3.9
IOCB Port B I/O Control, External LCD Driver Interface (for EMC 65x132) .....53 7.3.9.1 Page 0 Port B I/O Control .................................................................. 53 7.3.9.2 Page 1 External LCD Driver Controller.............................................. 53 7.3.10 IOCC Port C I/O Control, Port 6 Pull-high Register ..........................................56 7.3.10.1 Page 0 Port C I/O Control .................................................................. 56 7.3.10.2 Page 1 Port 6 Pull-high Register ....................................................... 56 7.3.11 IOCD Port D I/O Control, Port 7 Pull-high Register ..........................................56 7.3.11.1 Page 0 Port D I/O Control .................................................................. 56 7.3.11.2 Page 1 Port 7 Pull-high Register ....................................................... 57
Product Specification (V2.4) 02.17.2006
v
Contents
7.3.12 IOCE Interrupt Mask, Differential Energy Detect ..............................................57 7.3.12.1 Page 0 Interrupt Mask Register 1 ...................................................... 57 7.3.12.2 Page 1 Differential Energy Detect...................................................... 57 7.3.13 IOCF Interrupt Mask Register 2 ........................................................................58
7.4 7.5 7.6 7.7 7.8 7.9
I/O Port..............................................................................................................59 Reset.................................................................................................................60 Wake-up............................................................................................................61 Interrupt.............................................................................................................61 Instruction Set ...................................................................................................61 Code Option Register .......................................................................................63
7.9.1 Code Option Register 1 (Program ROM)..........................................................63 7.10 Call Waiting Function Description .....................................................................64 8 9 10 11 12 7.11 Differential Energy Detector (DED) ...................................................................65 Absolute Maximum Ratings ................................................................................... 66 DC Electrical Characteristic ................................................................................... 66 AC Electrical Characteristic ................................................................................... 67 Timing Diagrams ..................................................................................................... 71 Application Circuit .................................................................................................. 74
APPENDIX
A Application Note...................................................................................................... 75
Specification Revision History
Doc. Version 1.0 1.1 Initial version Changed the FSK, DTMF and CW Power Control 1. 2.0 2. 3. 1. 2.1 2. 3. 4. 2.2 2.3 2.4 Removed the 256K byte data ROM Removed the expand program/data memory interface Embedded 1.2%, 2.0% and 5.5% CAS frequency range deviation Added 256K byte data ROM Added expand program/data memory interface Removed 1.2% CAS frequency range deviation Removed UART function 2003/08/19 2003/10/08 2006/02/17 2003/03/04 Revision Description Date
Modified the Current DA resolution from 7 bit to 10 bit Added UART function 1. 2. Removed Idle mode Added application note item 7
vi *
Product Specification (V2.4) 02.17.2006
EM78815 8-Bit Microcontroller
1
General Description
The EM78815 is an 8-bit CID (Call Identification) RISC type microprocessor with low power, high speed CMOS technology. Integrated onto a single chip are on chip watchdog (WDT), programmable real time clock/counter, external/internal interrupt, power down mode, EMC65132 LCD controller, FSK decoder, Call waiting decoder, Energy Detector (DED) , DTMF receiver, Programming Tone generator, build-in Keytone clock generation, Comparator and tri-state I/O. The EM78815 provides a single chip solution to design a CID of calling message display.
2
Features
2.1 CPU
Operating voltage range: 2.2V~3.6V(Normal mode), 2.0V~3.6V(Green mode) 64Kx13 on-chip Program ROM, supports a max. of 128K word program 256Kx8 on-chip data ROM, supports a max. of 2M byte data 4Kx8 data RAM 128x8 common register Up to 56 bidirectional tri-state I/O ports IO with internal Pull high, wake-up and interrupt functions Stack: 24-level stack for subroutine nesting TCC: 8-bit real time clock/counter (TCC) with 8-bit prescaler Counter 1: 16 bit counter with 8-bit prescaler can be an interrupt source Counter 2: 8-bit counter with 8-bit prescaler can be an interrupt source Watchdog: Programmable free running on-chip watchdog timer CPU modes:
Mode Sleep mode Green mode Normal mode CPU Status Turn off Turn on Turn on Main Clock Turn off Turn off Turn on 32.768kHz Clock Status Turn off Turn on Turn on
15 interrupt source: 8 external, 7 internal Key Scan: Port key scan function up to 16x4 keys Sub-Clock: 32.768kHz crystal Main-clock: 3.5862MHz multiplied by 0.5, 1, 1.5 or 3 generated by internal PLL Keytone output: 4kHz, 2kHz, 1kHz (shared with IO) Comparator: 3-channel comparators, internal (16 level) or external reference voltage (shared with IO)
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
*1
EM78815 8-Bit Microcontroller
2.2 Serial Transmitter/Receiver Interface
Serial Peripheral Interface (SPI): Interrupt flag available for the read buffer full, Programmable baud rates of communication, Three-wire synchronous communication (shared with IO) Universal asynchronous receiver transmitter interface. User can select (7/8/9 bits) with/without parity bit, Baud rate setting and error detection function. Interrupt available for RX buffer full or TX buffer empty. Two wire asynchronous communication (shared with IO)
2.3 Current D/A
Operating Voltage: 2.5V~3.6V 10-bit resolution and 3-bit output level control Current DA output can drive the speaker through a transistor for sound playing. (shared with IO)
2.4 Programmable Tone Generators
Operating Voltage: 2.2V~3.6V Programmable Tone 1 and Tone 2 generators Independent single tone generation for Tone 1 and Tone 2 Mixed dual tone generation by Tone 1 and Tone 2 with 2dB difference Can be programmed for DTMF tone generation Can be programmed for FSK signal (Bell202 or V.23) generation
2.5 CID
Operating Voltage: 2.4V~3.6V for FSK Operating Voltage: 2.4V~3.6V for DTMF receiver Compatible with Bellcore GR-30-Core (formerly as TR-NWT-000030) Compatible with British Telecom (BT) SIN227 & SIN242 FSK demodulator for Bell 202 and ITU-T V.23 (formerly as CCITT V.23) Differential Energy Detector (DED) for line energy detection
2*
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
2.6 Call Waiting
Operating Voltage: 2.4V~3.6V Compatible with Bellcore special report SR-TSV-002476 Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector Good talk-down and talk-off performance Sensitivity compensated by adjusting input OP gain
2.7 External LCD controller (64 x 256 dot max for a pair of Master and Slave LCD Driver)
Multi-chip operation (Master, Slave) available for external LCD device
2.8 Package Type
105-pin Chip: EM78815H 128-pin QFP: (EM78815AQ, POVD disable) (EM78815BQ, POVD enable)
3
Application
SMS phone Feature phones
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
3
EM78815 8-Bit Microcontroller
4
Pin Configuration
EXD2 EXD3 EXD4 EXD5 EXD6 EXD7 RD WR CS EXA0 EXA1 EXA2 EXA3 EXA4 EXA5 EXA6 EXA7 EXA8 EXA9 EXA10 EXA11 EXA12 EXA13 EXA14 EXA15 EXA16 EXA17 EXA18 EXA19 EXA20 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 AVDD PLLC TONE TIP RING CWGS CWIN EGIN1 EGIN2 AVSS P60/STGT P61/EST P62 P63 P64 P65CMP1 P66/CMP2 P67/CMP3 PD0 PD1 PD2/UR PD3/UT PD4/SCK PD5/SDO PD6/SDI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 EXD1 EXD0 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PB0/LD0 PB1/LD1 PB2/LD2 PB3/LD3 PB4/LD4 PB5/LD5 PB6/LD6 PD7/DAOUT VDD XIN XOUT /RESET P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74/INT4 P75/INT5 P76/INT6/KTONE P77/INT7 EXSEL GND TEST PC7 PC6 PC5 PC4/A0 PC3/RD PC2/WR PC1/CS1 PC0/CS2 PB7/LD7
Fig.1a 105-pin Chip Assignment
4*
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
CS EXA0 NC NC NC NC NC NC EXA1 EXA2 EXA3 EXA4 EXA5 EXA6 EXA7 EXA8 EXA9 EXA10 EXA11 EXA12 EXA13 EXA14 EXA15 EXA16 EXA17 EXA18 EXA19 EXA20 AVDD PLLC TONE TIP 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
NC NC NC NC NC NC P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74/INT4 P75/INT5 P76/INT6/KTONE P77/INT7 EXSEL GND TEST PC7 PC6 PC5 PC4/A0 PC3/RD PC2/WR PC1/CS1 PC0/CS2 PB7/LD7 PB6/LD6 PB5/LD5 PB4/LD4 PB3/LD3 NC NC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
NC NC NC RING CWGS CWIN EGIN1 EGIN2 AVSS P60/STGT P61/EST P62 P63 P64 P65CMP1 P66/CMP2 P67/CMP3 PD0 PD1 PD2 PD3 PD4/SCK PD5/SDO PD6/SDI PD7/DAOUT VDD VDD XIN XOUT /RESET NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
WR RD EXD7 EXD6 EXD5 EXD4 EXD3 EXD2 EXD1 EXD0 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PB0/LD0 PB1/LD1 PB2/LD2 NC NC NC
Fig. 1b 128-pin QFP Assignment
5
EM78815 8-Bit Microcontroller
5
Functional Block Diagram
VDD
P ro g ra m ROM D a ta D ATA RAM D ATA ROM
S e ria l IO
MCU
GND AVDD TO NE DTMF s ig n a l CAS FSK s ig n a l FSK DTM F CAS s ig n a l Dual Tone G e n e ra to r DTM F R e c e iv e r CW D ecoder FSK D ecoder E n e rg y D e te c to r C u rre n t DA DAOUT PLL
C o m p a ra to r
A n a lo g in p u t
AVSS
Fig. 2 Block Diagram 1
Xin Xout PLLC WDT Timer Oscillator Timing Control R1 (TCC) Control sleep and wake-up on I/O port General RAM R4 Interrupt Control Prescalar Instruction Register R3 R5 ALU ROM R2 Stack
ACC
Instruction Decoder
Data & Control Bus
Data RAM Port 6 FSK Decoder Call Waiting Decoder DTMF DUAL TONE DTMF Receiver receiver GENERATOR Dual Tone Generator Keytone TONE KEY Serial I/O SERIAL I/O COMPARATO Comparator Current R DA Energy Detect IOC6 R6 Port 7 IOC7 R7 Port 8 IOC8 R8 Port 9 IOC9 R9 Port B IOCB RB Port C IOCC RC Port D IOCD RD
P60~P67
P70~P77 P80~P87
P90~P97 PB0~PB7 PC0~PC7 PD0~PD7
Fig. 3 Block Diagram 2
6*
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
6
Pin Descriptions
6.1 Power Pin
Pin VDD AVDD GND AVSS I/O Power Power Power Power Digital Power Analog Power Digital Ground Analog Ground Description
6.2 Clock Pin
Pin XIN XOUT PLLC I/O I O I Description Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase lock loop capacitor, connect a 0.01 capacitor to 0.047 with GND.
6.3 External LCD Device Control Pin
Pin LCDD0~LCDD7 /WR /RD A0 /CS1 ~ /CS2 I/O I/O O O O O Description External LCD driver data bus. This is pin-shared with Port B0~Port B7. Write enable output (active low signal). This is pin-shared with Port C2. Read enable output (active low signal). This is pin-shared with Port C3. Used as register selection. When A0 is equal to 1, the data bus transmits LCD Data. When A0 is equal to 0, the data bus transmits LCD Address. This is pin-shared with Port C4. Chip Select signal output. This is pin-shared with Port C1~ Port C0
6.4 FSK, CW
Pin TIP RING CWGS CWIN I/O I I O I Description Should be connected to the TIP side of the twisted pair lines for FSK. Should be connected to the RING side of the twisted pair lines for FSK. Gain adjustment of single-ended input OP Amp. Single-ended input OP Amp for call waiting decoder.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
7
EM78815 8-Bit Microcontroller
6.5 DTMF Receiver, OP
Pin I/O Description Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause the EST to return to a logic low. This is pinshared with Port 61. Steering input/guard time output (bi-directional). A voltage greater than Vtst detected at ST causes the device to register the detected tone-pair and update the output latch. A voltage less than Vtst frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of EST and the voltage on ST. This is pin-shared with Port 60.
EST
O
STGT
I/O
6.6 Serial IO, Comparator, Current DA, Tone
Pin SCK SDO SDI UR UT CMP1 CMP2 CMP3 DAOUT KTONE TONE I/O I/O O I I O I I I O O O Description Master: output pin, Slave: input pin. This is pin-shared with Port D4. Output pin for serial data transferring. This is pin-shared with Port D5. Input pin for receiving data. This is pin-shared with Port D6. Data receiver pin for UART. This pin shared with Port D2 Data transmitter pin for UART. This is pin-shared with Port D3. Comparator input pins. This is pin-shared with Port 65. Comparator input pins. This is pin-shared with Port 66 Comparator input pins. This is pin-shared with Port 67. Current DA output pin. It can be a control signal for sound generation. This is pin-shared with Port D7. Key tone output. This is pin-shared with Port 76. Dual tone output pin
6.7 IO
Pin P60 ~P67 P70 ~ P77 P80 ~ P87 P90 ~ P97 PB0 ~ PB7 PC0 ~ PC7 PD0 ~ PD7 P70 ~ P76 I/O I/O I/O I/O I/O I/O I/O I/O I Description Each bit in Port 6 can be Input or Output port. Internal pull high. Each bit in Port 7 can be Input or Output port. Internal Pull high function, Auto key scan function, and Interrupt function. Each bit in Port 8 can be Input or Output port. Each bit in Port 9 can be Input or Output port. Each bit in Port B can be Input or Output port. Each bit in Port C can be Input or Output port. Each bit in Port D can be Input or Output port. This is pin-shared with SPI pin and CMP input pin. Interrupt sources. When any pin from Port 70 to Port 76 has a falling edge signal, it will generate a corresponding interrupt. Interrupt source. Once Port 77 has a falling edge or rising edge signal (controlled by CONT register), it will generate an interrupt. Low reset
P77 /RESET
I I
8*
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
6.8 Expand Program/Data ROM Interface
Pin EXD0 ~ EXD7 /RD /WR /CS EX0~EXA20 EXSEL I/O I/O O O O O I Description Expand Program/Data memory Data Bus Expand Program/Data memory Read request output Expand Program/Data memory Write request output Expand Program/Data memory CS request output Expand Program/Data memory Address Bus 0/1 Internal 64K Program ROM used/unused
EXSEL pin : 0/1 On-chip program ROM used/unused switch. The EM78815 supports a max. of 128K Program. User can support program for both 64K EM78815 on-chip ROM and 64K expanded ROM. User can also ignore the 64K EM78815 on-chip ROM and support all programs for an external 128K ROM. Using this function, user can easily upgrade programs or download new functions. The EM78815 provides Data ROM expanded function. When user access data of which address is over 256K, the external ROM will be loaded. User must set the expanded start address of the Data ROM to RF Page 1, Page 2 and IOCB Page 1. A diagram of the expanded function is shown below.
Max. of 2M Byte Expanded ROM (FLASH ROM) Expanded Data ROM Start Address 64K Program ROM (Page 0 ~ Page 63) IOCB B7 B7 RF Page 2 B0 B7 RF Page 1 B0
64K word Program ROM (Page 64 ~ Page127
00 0 XXXXXXXXXXXXXXXXX0 ROM Address 0
ROM Address 17 256K Byte Data ROM Expanded Data ROM
ROM Address 9
EM78815 (EXSEL pin go low)
Fig. 4a EXSEL = 0, Both Internal and External Programs are Used
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
9
EM78815 8-Bit Microcontroller
Max. of 2M Byte Expanded ROM (FLASH ROM) Expanded Data ROM Start Address 64K Program ROM Unused IOCB B7 B7 RF Page 2 B0 B7 RF Page 1 B0
128K word Program ROM (Page 0 ~ Page 127)
000 XXXXXXXXXXXXXXXXX0
ROM Address 17 256K byte Data ROM Expanded Data ROM
ROM Address 9
ROM Address 0
EM78815 (EXSEL pin pull high)
Fig. 4b EXSEL = 1, Only External Program is Used
Setting the expanded Data ROM's Starting Address The EM78815 supports a maximum of 2M Bytes expanding data memory, but user must fix the start address of the external program at 0x00000 and set the start address of the expanded Data ROM since the program ROM size is adjustable. In this way, the MCU will get data from the external memory if the data ROM is over 256K. The instruction width is 13 bits and the data bus for external memory is 8 bits, so an instruction will capture two address sizes and the LSB address of the start address at the external ROM will be 0. Besides, the EM78815 only supports a max of 128K program, so the start address of the Data ROM will be smaller than 256K+2 and A20, A19 and A18 will also be 0. User must set the expanded start address of the Data ROM at A17~A1 to IOCB Page 2, Bit 7, RF Page 3 and RF Page 2.
10 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7
Function Description
7.1 Operational Register
REGISTER PAGE0 Address REGISTER PAGE1 REGISTER PAGE2 REGISTER PAGE3 Control REGISTER PAGE0 Control REGISTER PAGE1
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : R4 P1(7,8) 3F
R1 (TCC Buffer) R2 (PC)
R1 (Real Interrupt Flag 1)
R1 (Real Interrupt Flag 2) R1 (UART Receiver Buffer)
R3 (6, 7) R3 (STATUS) R4 (RSR, Bank Select) R5 (Program Page) R6 (Port 6 IO data) R7 (Port 7 IO data) R8 (Port 8 IO data) R9 (Port 9 IO data) RA (Power saving , FSK) RB (Port B IO data) RC (Port C IO data) RD (Port D IO data) RE (Interrupt Flag 1) RF (Interrupt Flag 2) R4 (Unused) R5 (Counter Setting) R6 (DROM Data Buffer) R7 (DROM Address) R8 (DROM Address) R9 (DROM Address) RA (Unused) RB (Unused) RC (DRAM1 Data Buffer) RD (DRAM1 Address) RE (DRAM 1 Address, DED Output ) RF (External Data ROM Start Address Low) R4 (UART Control 1) R5 (CNT1 low 8-bit data) R6 (CNT1 high 8-bit data) R7 (CNT2 data) R8 (DTMF receiver) R9 (CMP IO control) RA (Comparator Control) RB (Key Strobe Control) RC (Key Strobe Control) RD (Unused) RE (Key Scan , CAS) RF (External Data ROM Start Address High) R4 (UART Contro l2) R5 (Current DA Control) R6 (Current DA Control) R7 (SPI Control) R8 (SPI Data Buffer) R9 (Keytone Control, UART MSB) RA (Tone 1 Control) RB (Tone 2 Control) RC (Unused) RD (Unused) RE (Unused) RF (Unused)
R3 (5)
IOC5 (Address auto inc/dec Control) IOC6 (Port 6 I/O Control) IOC7 (Port 7 I/O Control) IOC8 (Port 8 I/O Control) IOC9 (Port 9 I/O Control) IOCA (Stack Pointer) IOCB (Port B I/O control)
IOC5 (DRAM2 Data Buffer) IOC6 (DRAM2 Address) IOC7 (DRAM2 Address) IOC8 (Unused) IOC9 (Unused) IOCA (Unused) IOCB (External LCD Driver Control Interface)
IOCC (Port C I/O Control) IOCC (P6 Pull-high Control) IOCD (Port D I/O Control) IOCD (P7 Pull-high Control) IOCE (Interrupt Mask 1) IOCE (Interrupt Mask 2) IOCE (DED Control)
16 Byte Commom register
Bank0 32x8
Bank1 32x8
Bank2 32x8
Bank3 32x8
DATA ROM R7 PAGE1 : address(L) R8 PAGE1 : address(M) R9 PAGE1 : address(H) R6 PAGE1 : data
DATA RAM (Index 1) RD PAGE1 : address(L) RE PAGE1 : address(H) RC PAGE1 : data
DATA RAM (Index2) IOC6 PAGE1 : address(L) IOC7 PAGE1 : address(H) IOC5 PAGE1 : data
Commom register
Fig. 5 Control Register Configuration
7.2 Operational Register Detail Description
7.2.1 R0 Indirect Addressing Register
R0 is not a physically implemented register. It is provided as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed to by the RAM Select Register (R4). Example: mov mov mov mov A , @0x20 ;store an address at R4 for indirect ;addressing ;write data 0xAA to R20 at Bank 0 ;through R0
0x04 , A A , @0xAA 0x00 , A
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
11
EM78815 8-Bit Microcontroller
7.2.2 R1 Page 0 TCC Data Buffer
This is increased by 16.38 kHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register.
7.2.3 R1 Page 1 Interrupt Flag 1 Real Value
Bit 7 INTR7 R/W-0 Bit 6 INTR6 R/W-0 Bit 5 INTR5 R/W-0 Bit 4 INTR4 R/W-0 Bit 3 INTR3 R/W-0 Bit 2 INTR2 R/W-0 Bit 1 INTR1 R/W-0 Bit 0 INTR0 R/W-0
Bit 0~Bit 7(INTR0~INTR7) : Interrupt Flag 1 real value. User can clear this page from 1 to 0 but cannot set this register to 1. The relation of R1 Page1, RE Page 0 and IOCE Page 0 is shown in the figure. When user disables the interrupt mask, whether an interrupt occurs or not, the interrupt flag (RE Page 0) will appear "0". Opposite of RE Page 0, R1 Page 1 will show real interrupt occur status regardless whether this interrupt mask is enabled or disabled. User can clear the corresponding external interrupt flag in RE Page 0 or R1 Page 1.
Interrupt occurs
Interrupt Mask IOCE, IOCF
Interrupt Flag (RE, RF) Real Interrupt Flag (R0 P1,P2)
Fig. 6 Relationship between Interrupt Mask, Flag and Real Flag
7.2.4 R1 Page 2 Interrupt Flag 2 Real Value
Bit 7 RBF/STD R/W-0 Bit 6 FSK/CW R/W-0 Bit 5 R/W-0 Bit 4 UART R/W-0 Bit 3 DED R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCC R/W-0
Bit 0~Bit 7 (Internal Interrupt Flag Real Value) : Interrupt Flag 1 real value. User can clear this page from 1 to 0 but cannot set this register to 1. The relationship between R1 Page 2, RF Page 0 and IOCF Page 0 is shown in Fig. 6. When user disables an interrupt mask, whether an interrupt occurs or not, the interrupt flag (RF Page 0) will appear "0". Opposite of RF Page 0, R1 Page 1 will show real interrupt occur status regardless whether this interrupt mask is enabled or disabled. User can clear the corresponding interrupt flag in RF Page 0 or R1 Page 2.
12 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.2.5 R1 Page 3 UART Receiver Data Buffer
Bit 7 URR7 R Bit 6 URR6 R Bit 5 URR5 R Bit 4 URR4 R Bit 3 URR3 R Bit 2 URR2 R Bit 1 URR1 R Bit 0 URR0 R
Bit 0~Bit 7(URR0~URR7) : UART receiver low 8 bit data buffer. UART receiver data buffer is a read-only register.
7.2.6 R2 Program Counter
There are 128K x 13 External Program ROM addresses at the relative programming instruction codes. The structure is depicted on Fig. 5. "JMP" instruction allows a direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then pushed into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits do not change. The most significant bit (A10~A14) will be loaded with the contents of bits PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2,A'' instruction. If there is an interrupt trigger, the Program ROM will jump to Address 8 at Page 0. The CPU will store ACC, R3 status and R5 Page automatically, it will restore after instruction RETI.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
13
EM78815 8-Bit Microcontroller
R5(PAGE)
CALL and INTERRUPT A9 A8 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 : : STACK22 STACK23 STACK24 1111110 PAGE126 1F800~1FBFF 1111111 PAGE127 1FC00~1FFFF
A16 A15 A14 A13 A12 A11 A10
0000000 PAGE0 00000~003FF 0000001 PAGE1 00400~007FF 0000010 PAGE2 00800~00BFF
store ACC,R3,R5(PAGE) restore
Fig. 7 Program Counter Organization
7.2.7 R3 Status Register
Bit 7 RS1 R/W-0 Bit 6 RS0 R/W-0 Bit 5 IOCS R/W-0 Bit 4 T R/W-X Bit 3 P R/W-X Bit 2 Z R/W-X Bit 1 DC R/W-X Bit 0 C R/W-X
Bit 0 (C) :
Carry
Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Bit 3 (P) : Zero flag Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) : Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
Event WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 P 0 1 0 1 Remark
x
x
x: don't care
14 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 5 (IOCS) : IOC register select bit. Change IOC5 ~ IOCE to another page Bit 6~Bir 7 (RS0 ~ RS1) : R register select bits. Change R1, R2, R4 ~ RE to another page.
RS1 0 0 1 1 RS0 0 1 0 1 R Page Page 0 Page 1 Page 2 Page 3
7.2.8 R4 RAM Select for Common Registers R20~R3F, UART Control Register
7.2.8.1 Page 0
Bit 7 RBS1 R/W-0 Bit 6 RBS0 R/W-0 Bit 5 RSR5 R/W-X Bit 4 RSR4 R/W-X Bit 3 RSR3 R/W-X Bit 2 RSR2 R/W-X Bit 1 RSR1 R/W-X Bit 0 RSR0 R/W-X
Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks of the 32 registers (R20 to R3F). Refer to Fig. 4 Control Register Configuration for details. 7.2.8.2 Page 1 Undefined Register This register is unimplemented, not for use.
7.2.9 Page 2 UART Control Register 1
Bit 7 TRS2 Bit 6 TRS1 Bit 5 TRS0 Bit 4 URM1 Bit 3 URM0 Bit 2 ERE Bit 1 TXE Bit 0 RXE
Bit 0 (RXE) : Enable UART receiving function & UART interrupt mask 1 Enable 0 Disable Bit 1 (TXE) : Enable UART transmission function & UART interrupt mask 1 Enable 0 Disable Bit 2 (ERE) : Enable UART receiver error interrupt mask
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
15
EM78815 8-Bit Microcontroller
ERR
TXE 0 0 0 1 1 1
REX 0 1 1 0 1 1
RF Bit 4 (UART) Interrupt Trigger Event UART interrupt disable UART read buffer full UART read buffer full or Receiver Data Error UART transmitter buffer empty UART read buffer full or UART transmitter buffer empty UART read buffer full or UART transmitter buffer empty or Receiver Data Error PD2 PD3 PD2 PD3 PD2 PD3 PD2 PD3 PD2 PD3
I/O Status IO IO UART receiver pin IO UART receiver pin IO IO UART transmitter pin UART receiver pin UART transmitter pin
x
0 1
x
0 1
PD2 UART receiver pin PD3 UART transmitter pin
Bit 4~Bit 3 (URM1~URM0) : UART Mode Select
URM1 0 0 1 1 URM0 0 1 0 1 Mode Status 7 bit data 8 bit data 9 bit data
x
Bit 7~Bit 5 (TRS2~TRS0) : Baud Rate Select
TRS2 0 0 0 0 1 1 1 1 TRS1 0 0 1 1 0 0 1 1 TRS0 0 1 0 1 0 1 0 1 Baud Rate 600 baud 1200 baud 2400 baud 9600 baud 19200 baud 38400 baud 57600 baud 115200 baud
Note: 600 and 1200 baud rates can be run in green mode
7.2.10 Page 3 UART Control Register 2
Bit 7 - Bit 6 EVEN R/W-X Bit 5 PRE R/W-0 Bit 4 PRERR R/W-0 Bit 3 OVERR R/W-0 Bit 2 FMERR R/W-0 Bit 1 UTBE R Bit 0 URBF R
x
Bit 0 (URBF) : UART read buffer full flag . Set to 1 when one character is received. Reset to 0 automatically when read from UART data buffer.
16 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 1 (UTBE) : UART transfer buffer empty flag. Set to 1 when transfer buffer is empty. Reset to 0 automatically when writing into the UART data buffer. Bit 2 (FMERR) : Receiver error flag . Set to 1 when frame error occurs. Clear this bit to 0 by software. Bit 3 (OVERR) : Receiver error flag . Set to 1 when over running error occurs. Clear this bit to 0 by software. Bit 4 (PRERR) : Receiver error flag . Set to 1 when parity error occurs. Clear this bit to 0 by software. Bit 5 (PRE) : Enable parity addition 1 Enable 0 Disable Bit 6(EVEN) : EVEN/ODD parity check select 1 Even parity 0 Odd parity In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. The figure below shows the general format of one character sent or received. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit. If present, then the stop bit or bits (high) confirm the end of the frame. In receiving, the UART synchronizes on the falling edge of the start bit. When two or more "0" are detected during 3 samples, it is recognized as normal start bit and the receiving operation is started.
START bit
D0
D1
D2
Dn
Parity STOP bit bit
Idle state (mark)
1 bit
7 or 8 bits One character or frame
1 bit
1 bits
Fig. 8 UART Data Frame
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
17
EM78815 8-Bit Microcontroller
There are three modes in UART. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the addition of a parity bit. The parity bit addition is not available in Mode 3. The Figure below shows the data format in each mode.
UMODE
PRE 0 1
1
START
2
3
4
5
6
7
8
9
STOP
10
11
Mode 1
0 0
0 0
7 bits DATA 7 bits DATA
START
Parity
STOP
Mode 2
0 0
1 1
0 1
START
8 bits DATA 8 bits DATA
STOP
START
Parity STOP
Mode 3
1
0
X
START
9 bits DATA
STOP
Fig. 9 UART Mode
In transmitting serial data, the UART operates as follows. 1. Set TXE bit of the UARTCON register to enable the UART transmission function. 2. Write data into the UART data buffer. Then start transmitting. 3. Serial transmit data are transmitted in the following order from UT (Port C7) pin. (a) Start bit: output one "0" bit (b) Transmit data: 7, 8 or 9 bits data are output from LSB to MSB (c) Parity bit: output one parity bit (odd or even selectable)
(d) Stop bit: output one "1" bit (stop bit) (e) Mark state: output "1" continues until the start bit of the next transmit data 4. After transmitting the stop bit, the UART generates a UART interrupt (if enabled) 5. UTBE bit will be set to 1 In receiving, the UART operates as follows: 1. Set the RXE bit of the UARTCON register to enable the UART receiving function. The UART monitors the UR (Port C6) pin and synchronizes internally when it detects a start bit. 2. Receive data is shifted into the UARTRx register in the order from LSB to MSB.
18 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
3. The parity bit and the stop bit are received. After one character is received, the UART generates a UART interrupt (if enabled). URBF bit will be set to 1. 4. The UART makes the following checks: (a) Parity check: The number of 1 in receive data must match the even or odd parity setting of the EVEN bit in the UARTSTA register. (b) Frame check: The start bit must be 0 and the stop bit must be 1. (c) Overrun check: URBF bit of UARTCON register must be cleared (which means that the UARTRx register should be read out) before the next received data is loaded into the UARTRx register. If any checks failed, a UART interrupt will be generated (if enabled). The error flag should be cleared by software else a UART interrupt will occur when the next byte is received. 5. Read received data from the UART register. URBF bit will be cleared by hardware.
Selector Baud rate generator
Fsystem
RXE
RX Control
Interrupt Control
TX Control
TXE
RXD
RX shift register
Parity control
TXD
UINVEN
URR8
URR7~URR0
Error flag
URT8
URT7~URT0
Data Bus
UINVEN
Fig. 10 UART Function Block
Bit 7 : Unused
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
19
EM78815 8-Bit Microcontroller
7.2.11 R5 Program Page Selection, CNT CLK & Scale Setting, CNT1 Data (L)
7.2.11.1 Page 0 Program Page
Bit 7 Bit 6 PS6 R/W-0 Bit 5 PS5 R/W-0 Bit 4 PS4 R/W-0 Bit 3 PS3 R/W-0 Bit 2 PS2 R/W-0 Bit 1 PS1 R/W-0 Bit 0 PS0 R/W-0
x
Bit 0 ~ Bit 6 (PS0 ~ PS6) : Program page selection bits
PS6 0 0 0 0 PS5 0 0 0 0 PS4 0 0 0 0 : : 1 1 1 1 1 1 PS3 0 0 0 0 : : 1 1 PS2 0 0 0 0 : : 1 1 PS1 0 0 1 1 : : 1 1 PS0 0 1 0 1 : : 0 1 Program Memory Page (Address) Page 0 Page 1 Page 2 Page 3 : : Page 126 Page 127
User can use the Page instruction to change page and maintain user's program page. Bit 7 : This bit is undefined, not for use. 7.2.11.2 Page 1 Counter 1 Counter 2 CLK and Scale Setting
Bit 7 CNT2S R/W-0 Bit 6 C2P2 R/W-0 Bit 5 C2P1 R/W-0 Bit 4 C2P0 R/W-0 Bit 3 CNT1S R/W-0 Bit 2 C1P2 R/W-0 Bit 1 C1P1 R/W-0 Bit 0 C1P0 R/W-0
Bit 0~Bit 2(C1P0~C1P2) : Counter 1 scaling
C1P2 0 0 0 0 1 1 1 1 C1P1 0 0 1 1 0 0 1 1 C1P0 0 1 0 1 0 1 0 1 Counter 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (CNT1S) : Counter 1 clock source 0/1 16.384kHz/instruction clock
20 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 4~Bit 6 (C2P0~C2P2) : Counter 2 scaling. Prescaler is different for Bit 0~Bit 2.
C2P2 0 0 0 0 1 1 1 1 C2P1 0 0 1 1 0 0 1 1 C2P0 0 1 0 1 0 1 0 1 Counter 2 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 7 (CNT2S) : Counter 2 clock source 0/1 16.384kHz / instruction clock 7.2.11.3 Page 2 Counter 1 Low 8-bit Data Buffer
Bit 7 CN17 R/W-0 Bit 6 CN16 R/W-0 Bit 5 CN15 R/W-0 Bit 4 CN14 R/W-0 Bit 3 CN13 R/W-0 Bit 2 CN12 R/W-0 Bit 1 CN11 R/W-0 Bit 0 CN10 R/W-0
Bit 0~Bit 7 (CN10~CN17) : Counter 1 data buffer Counter 1 is a 16 bits up-counter with 8-bit prescaler and user can read or write into the counter through R5 Page 2 and R6 Page 2. After an interrupt, it will reload the preset value. Example: write: MOV 0x05,A ; write the accumulator data to Counter 1 (preset) Example: read: MOV A,0x05 ; read R5 data and write into the accumulator Example: write: MOV 0x06,A ; write the accumulator data (high 8 bits) to Counter 1 Example: read: MOV A,0x06 ; read R6 data (high 8 bits) and write into the accumulator 7.2.11.4 Page 3 DA Control
Bit 7 - - Bit 6 - - Bit 5 - - Bit 4 - - Bit 3 CDAS R/W-0 Bit 2 CDAL2 R/W-0 Bit 1 CDAL1 R/W-0 Bit 0 CDAL0 R/W-0
Bit 0 ~ Bit 2 (CDAL0 ~ CDAL2) : Change output level of the current DA
CDAL2 0 0 0 0 1 1 1 1 CDAL1 0 0 1 1 0 0 1 1 CDAL0 0 1 0 1 0 1 0 1 Output Level L0 (ratio = 1/8) L1 (ratio = 2/8) L2 (ratio = 3/8) L3 (ratio = 4/8) L4 (ratio = 5/8) L5 (ratio = 6/8) L6 (ratio = 7/8) L7 (ratio =1)
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
21
EM78815 8-Bit Microcontroller
Bit 3 (CDAS) : Current DA switch 0 normal Port D7 1 Current DA output Bit 4 ~ Bit 7 : Undefined Register. These bits are undefined and not for use.
7.2.12 R6 Port 6 I/O Data, Data ROM Data Buffer, CNT1 Data (H), DA Control
7.2.12.1 Page 0 Port 6 I/O Data
Bit 7 P67 R/W-X Bit 6 P66 R/W-X Bit 5 P65 R/W-X Bit 4 P64 R/W-X Bit 3 P63 R/W-X Bit 2 P62 R/W-X Bit 1 P61 R/W-X Bit 0 P60 R/W-X
Bit 0 ~ Bit 7 (P60 ~ P67) : 8-bit Port 6 (0~7) I/O data register User can use IOC register to define whether each bit is input or output. 7.2.12.2 Page 1 Data ROM Data Buffer
Bit 7 DRD7 R Bit 6 DRD6 R Bit 5 DRD5 R Bit 4 DRD4 R Bit 3 DRD3 R Bit 2 DRD2 R Bit 1 DRD1 R Bit 0 DRD0 R
Bit 0 ~ Bit 7 (DRD0 ~ DRD7) : Data ROM data buffer for ROM reading. Example. MOV MOV MOV MOV MOV MOV MOV A,@1 R7_PAGE1,A A,@0 R8_PAGE1,A A,@0 R9_PAGE1,A A,R6_PAGE1 ;read the data at the Data ROM, of which ;address is "00001".
7.2.12.3 Page 2 Counter 1 High 8-bit Data Buffer
Bit 7 CN1F R/W-0 Bit 6 CN1E R/W-0 Bit 5 CN1D R/W-0 Bit 4 CN1C R/W-0 Bit 3 CN1B R/W-0 Bit 2 CN1A R/W-0 Bit 1 CN19 R/W-0 Bit 0 CN18 R/W-0
Bit 0~Bit 7 (CN18~CN1F) : Counter 1 high 8 bits data buffer. Refer to R5 Page 2 Counter 1 low 8-bit data buffer for details.
22 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.2.12.4 Page 3 DA Control
Bit 7 DA9 R/W-0 Bit 6 DA8 R/W-0 Bit 5 DA7 R/W-0 Bit 4 DA6 R/W-0 Bit 3 DA5 R/W-0 Bit 2 DA4 R/W-0 Bit 1 DA3 R/W-0 Bit 0 DA2 R/W-0
Bit 0 ~ Bit 7 (DA2 ~ DA9) : Current DA most significant 8 bits of Current DA output buffer Combine these 8 bits and R9 Page 3 Bit 4~Bit 5, 2 bits as complete 10 bits Current DA output data. Control register Bit 3 is Current DA power control.
DA9..DA0
VDD
Current DA Circuit
DAOUT Port D7 Port D7 MUX
DAEN DAS
Fig 11 s Current DA structure
7.2.13 R7 Port 7 I/O Data, Data ROM Address, CNT2 Data, SPI Control
7.2.13.1 Page 0 Port 7 I/O Data
Bit 7 P77 R/W-X Bit 6 P76 R/W-X Bit 5 P75 R/W-X Bit 4 P74 R/W-X Bit 3 P73 R/W-X Bit 2 P72 R/W-X Bit 1 P71 R/W-X Bit 0 P70 R/W-X
Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit Port 7(0~7) I/O data register User can use the IOC register to define whether each bit is input or output. 7.2.13.2 Page 1 Data ROM Address
Bit 7 DRA7 R/W-X Bit 6 DRA6 R/W-X Bit 5 DRA5 R/W-X Bit 4 DRA4 R/W-X Bit 3 DRA3 R/W-X Bit 2 DRA2 R/W-X Bit 1 DRA1 R/W-X Bit 0 DRA0 R/W-X
Bit 0 ~ Bit 7 (DRA0 ~ DRA7) : Data ROM address ( 0~7 ) for ROM reading
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
23
EM78815 8-Bit Microcontroller
7.2.13.3 Page 2 Counter 2 Data Buffer
Bit 7 CN27 R/W-0 Bit 6 CN26 R/W-0 Bit 5 CN25 R/W-0 Bit 4 CN24 R/W-0 Bit 3 CN23 R/W-0 Bit 2 CN22 R/W-0 Bit 1 CN21 R/W-0 Bit 0 CN20 R/W-0
Bit 0~Bit 7(CN20~CN27) : Counter 2's data buffer User can read and write into this buffer. Counter 2 is an 8-bit up-counter with 8-bit prescaler that user can use R7 page2 to preset and read the counter (write = preset). After an interrupt, it will reload the preset value. Example: write: MOV 0x07 , A ; write the data at accumulator to counter1 (preset) Example: read: MOV A , 0x07 ; read R7 data and write to accumulator 7.2.13.4 Page 3 SPI Control Register
Bit 7 RBF R/W-0 Bit 6 SPIE R/W-0 Bit 5 SRO R/W-0 Bit 4 SE R/W-0 Bit 3 SCES R/W-0 Bit 2 SBR2 R/W-0 Bit 1 SBR1 R/W-0 Bit 0 SBR0 R/W-0
Fig.12 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted basing on the clock rate and the selected edge.
SDO Master Device R5 Page 1 SPIR register SPIW register
SDI Slave Device
SPIS Reg Bit 7 Bit 0
SDI
SDO
SPI module
SCK
SCK
Fig 12: Single SPI Master / Salve Communication
24 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits
SBR2 0 0 0 0 1 1 1 1 SBR1 0 0 1 1 0 0 1 1 SBR0 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Master Slave Baud Rate Fsco Fsco/2 Fsco/4 Fsco/8 Fsco/16 Fsco/32
x
Note: Fsco = CPU Instruction Clock
Example: If PLL enable and RA Page 0 (Bit 5, Bit 4) = (1, 1), instruction clock is 3.58 MHz/2 Fsco=3.5862MHz/2 If PLL enable and RA Page 0 (Bit 5, Bit 4) = (0, 0), instruction clock is 0.895 MHz/2 Fsco=0.895 MHz/2 If PLL disable, instruction clock is 32.768kHz/2 Fsco=32.768kHz/2. Bit 3 (SCES) : SPI clock edge selection bit 0 Data shifts out on a rising edge, and shifts in on falling edge. Data is hold during the low level. 1 Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level. Bit 4 (SE) : SPI shift enable bit 0 Reset as soon as the shifting is complete, and the next byte is ready to shift. 1 Start to shift, and remain a 1 while the current byte is still being transmitted.
NOTE This bit has to be reset by software.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
25
EM78815 8-Bit Microcontroller
Bit 5 (SRO) : SPI read overflow bit 0 No overflow 1 A new data is received while the previous data is still being hold in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users have to read the SPIB register even if only the transmission is implemented. Note that this can only occur in slave mode. Bit 6 (SPIE) : SPI enable bit 0 Disable SPI mode 1 Enable SPI mode Bit 7 (RBF) : SPI read buffer full flag 0 Receive is not finished yet, SPIB is empty. 1 Receive is finished, SPIB is full.
Read R5 RBF RBFI SPIWC
Write R5
SPIR reg.
SPIW reg.
set to 1 SPIE Buffer Full Detector
SDI
SDI/P62
M UX
SPIS reg.
PORT62 bit 0 SDO
shift right
bit 7
SDO/P61
SPIC reg. (R4 page1)
M UX
PORT61
Edge Select SPIE 0
3
SBR0 ~SBR2
SBR2~SBR0
3 2
Noise Filter
Clock Select
Tsco
16.38kHz
Prescaler 4, 8, 16, 32, 64, 128
Edge Select
SCK PORT60
MUX
SCK/P60
SCK
SPIE
Fig. 13 SPI Structure
26 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
SPIC reg : SPI control register SDO/P61 : Serial data out SDI/P62 : Serial data in SCK/P60 : Serial clock RBF : RBFI : Set by buffer full detector, and reset by software. Interrupt flag. Set by buffer full detector, and reset in software.
Buffer Full Detect : Set to 1, while an 8-bit shifting is complete. SE : SPIE : Loads the data in SPIW register, and begins to shift SPI control register
SPIS reg. :Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data is being written to, SPIS starts transmission / reception. The received data will be moved to the SPIR register, as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the RBFI (Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register is read. SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is completed. The SE bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2 ~ SBR0: Programs the clock frequency/rates and sources. Clock Select : Selects either the internal instruction clock or the external 16.338kHz clock as the shifting clock. Edge Select : Selects the appropriate clock edges by programming the SCES bit
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
27
EM78815 8-Bit Microcontroller
SCK
(SCES=0)
SCK
(SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SDO
SDI
RBF
Shift data in
Shift data out
Fig. 14 SPI Timing
Clear by software
7.2.14 R8 Port 8 I/O Data, Data ROM Address, DTMF Receiver, SPI Data
7.2.14.1 Page 0 Port 8 I/O Data
Bit 7 P87 R/W-X Bit 6 P86 R/W-X Bit 5 P85 R/W-X Bit 4 P84 R/W-X Bit 3 P83 R/W-X Bit 2 P82 R/W-X Bit 1 P81 R/W-X Bit 0 P80 R/W-X
Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit Port 8 ( 0~7 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.14.2 Page 1 Data ROM address
Bit 7 DRA15 R/W-X Bit 6 DRA14 R/W-X Bit 5 DRA13 R/W-X Bit 4 DRA12 R/W-X Bit 3 DRA11 R/W-X Bit 2 DRA10 R/W-X Bit 1 DRA9 R/W-X Bit 0 DRA8 R/W-X
Bit 0 ~ Bit 7 (DRA8 ~ DRA15) : Data ROM address ( 8~15 ) for ROM reading
28 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.2.14.3 Page 2 DTMF Receiver
Bit 7 CMPFLAG R Bit 6 STD R/W-0 Bit 5 - x Bit 4 - x Bit 3 Q4 R/W-0 Bit 2 Q2 R/W-0 Bit 1 Q1 R/W-0 Bit 0 Q0 R/W-0
Bit 0 ~ Bit 3 (Q1 ~ Q4) : DTMF receiver decoding data These provide the code corresponding to the last valid tone-pair received (see code table). The STD signal with steering output presents a logic high when a received tone-pair has been registered and the Q4 ~ Q1 output latch updated, and generates an interrupt (IOCF has enabled); returns to logic low when the voltage on ST/GT falls below Vtst.
F low 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Any
Note: "x" means unknown
F high 1209 1336 1477 1209 1336 1477 1209 1336 1477 1209 1336 1477 1633 1633 1633 1633 Any
Key 1 2 3 4 5 6 7 8 9 0 * # A B C D Any
DREN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Q4~Q1 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000
xxxx
Bit 4~Bit 5 : Undefined Register Bit 6 (STD) : Delayed steering output Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below Vtst. 0/1 Data invalid/data valid Be sure to open the main clock before using the DTMF receiver circuit. A logic "0, 0" applied to R5 Page 3 B 4 and B 3 will shut down power of the device to minimize the power consumption in standby mode. It stops functions of the filters.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
29
EM78815 8-Bit Microcontroller
In many situations not requiring independent selection of received and paused, the simple steering circuit is applicable. Component values are chosen according to the following formula: t REC = t DP + t GTP t ID = t DA + t GTA The value of t DP is a parameter of the device and t REC is the minimum signal duration to be recognized by the receiver. A 0.1 F value for C is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a t REC of 30mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (t GTP) and tone-absent (t GTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and inter digital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing t REC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. On the other hand, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be required.
VDD
VDD C ST/GT EST R
Fig. 15 DTMF Receiver Delay Time Control
30 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
TONE Tdp 5~20mS by S/W Tgtp 30mS Typ. ST/GT
TONE Tgta 30mS Typ.
EST
Vtst 1/2 VDD Tpq 8 uS Typ.
Q4..Q1
STD
LINE_ENG
Fig. 16 DTMF Receiver Timing
Bit 7 (CMPFLAG) : Comparator output flag 0 Input voltage < reference voltage 1 Input voltage > reference voltage
NOTE Refer to Sec. 7.2.16.3 RA Page 2 Comparator Control Register.
7.2.14.4 Page 3 SPI Data Buffer
Bit 7 SPIB7 R/W-X Bit 6 SPIB6 R/W-X Bit 5 SPIB5 R/W-X Bit 4 SPIB4 R/W-X Bit 3 SPIB3 R/W-X Bit 2 SPIB2 R/W-X Bit 1 SPIB1 R/W-X Bit 0 SPIB0 R/W-X
Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will be written to the SPIW register. If you read this data, it will read the data from the SPIR register. Refer to Fig. 9.
7.2.15 R9 Port 9 I/O Data, Data ROM Address, Keytone Control
7.2.15.1 Page 0 Port 9 I/O Data
Bit 7 P97 R/W-X Bit 6 P96 R/W-X Bit 5 P95 R/W-X Bit 4 P94 R/W-X Bit 3 P93 R/W-X Bit 2 P92 R/W-X Bit 1 P91 R/W-X Bit 0 P90 R/W-X
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
31
EM78815 8-Bit Microcontroller
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit Port 9 ( 0~7 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.15.2 Page 1 Data ROM Address
Bit 7 Bit 6 Bit 5 Bit 4 DRA20 R/W-X Bit 3 DRA19 R/W-X Bit 2 DRA18 R/W-X Bit 1 DRA17 R/W-X Bit 0 DRA16 R/W-X
Bit 0 ~ Bit 4 (DRA16 ~ DRA20) : Data ROM address (16~20) for ROM reading.. Bit 5~Bit 7 : Unused 7.2.15.3 Page 2 FSK/CW/DTMF Power Select
Bit 7 PCTRL1 R/W-0 Bit 6 PCTRL0 R/W-0 Bit 5 ADCS3 R/W-0 Bit 4 ADCS2 R/W-0 Bit 3 ADCS1 R/W-0 Bit 2 Bit 1 Bit 0 -
Bit 0 ~ Bit 1 : Unused Bit 3 ~ Bit 5(ADCS1 ~ ADCS3) : PORT65 ~ Port 67 normal IO / CMP input control bit. ADCSX = 1 Comparator input ADCSX = 0 Normal IO Bit 6~Bit 7 (PCTRL0~PCTRL1) : FSK and DTMF power control bits
PCTRL1 0 0 1 1 PCTRL0 0 1 0 1 Select FSK and DTMFr power off FSK power on DTMF receiver power on Cannot be used Relation Register RA Page 0 R8 Page 2 -
* Do not set both the bits to 1, or FSK and DTMF function will fail. * When User turns on the DTMF receiver power, Port 60 and Port 61 will switch to
/STGT and EST pin. 7.2.15.4 Page 3 Keytone Control
Bit 7 URT8 R/W-X Bit 6 URR8 R Bit 5 DA1 R/W-X Bit 4 DA0 R/W-X Bit 3 URINV R/W-X Bit 2 KT1 R/W-0 Bit 1 KT0 R/W-0 Bit 0 KTS R/W-0
Bit 0 (KTS) : Key tone output switch 0 Normal Port 76 1 Keytone output
32 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 1 ~ Bit 2 (KT0 ~ KT1) : Keytone output frequency and its power control
KT1 0 0 1 1 KT0 0 1 0 1 Keytone Frequency and Power 32.768kHz/32 = 1.024kHz clock and enable 32.768kHz/16 = 2.048kHz clock and enable 32.768kHz/8 = 4.096kHz clock and enable Power-off keytone
Bit 3 (URINV) : Enable UART TXD, RXD port inverse output 0 Disable UART TXD, RXD port inverse output 1 Enable UART TXD, RXD port inverse output Bit 4 ~ Bit 5 (DA0~DA1) : These two bits are the least significant bits of the Current DA. Combine R6 Page 3 and these 2 bits as complete 10 bits Current DA output data. Bit 6 (URR8) : MSB of UART receiver data buffer. Bit 7 (URT8) : MSB of UART transmitter data buffer.
7.2.16 RA CPU Power Saving, Main CLK Select, FSK, WDT Timer Comparator Control, Tone 1 Generator
7.2.16.1 Page 0 Power Saving, Main CLK Select, FSK, WDT Timer
Bit 7 0 R/W-0 Bit 6 PLLEN R/W-0 Bit 5 CLK1 R/W-0 Bit 4 CLK0 R/W-0 Bit 3 ROMRI R/W-0 Bit 2 FSKDATA R Bit 1 /CD R Bit 0 WDTEN R/W-0
Bit 0 (WDTEN) : Watchdog control register User can use WDTC instruction to clear the watchdog counter. The counter's clock source is 32768/2 Hz. If the prescaler is assigned to TCC, the Watchdog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler is assigned to WDT, the time out will be more times depending on the prescaler ratio. 0/1 disable/enable Bit 1 (/CD) : FSK carrier detect indication 0/1 Carrier Valid/Carrier Invalid It is a read only signal. If the FSK decoder detects the energy of the marked or space signal, the Carrier signal will go to low level. Otherwise it will go to high. Note that this should be in normal mode.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
33
EM78815 8-Bit Microcontroller
Bit 2 (FSKDATA) : FSK decoding data output It is a read only signal. If the FSK decodes the mark or space signal, it will output a high level signal or low level signal at this register. It is a raw data type. That means the decoder just decodes the signal and has no process on the FSK signal. Note that this should be in normal mode. User can use FSK data falling edge interrupt function to help in data decoding. Example: MOV IOW CLR ENI : 0 = Space data (2200 Hz) 1 = Mark data (1200 Hz) FSK block power is controlled by R5 Page 3 Bit 3, 4. When PCTRI1=0 and PCTRL0=1, FSK power is turned on. The relation between R5 Bit 3 to Bit 4 and RA Bit 1 to Bit 2 are shown in Fig.17. You have to power up the FSK decoder first, then wait for a setup time (Tsup) and check carrier signal (/CD). If the carrier is low, the program can process the FSK data. A,@01000000 IOCF RF ;wait for FSK data's falling edge ;enable FSK interrupt function
FIRST RING 2 SECONDS TIP/RING
0.5 SEC FSK signal Tcdl
0.5 SEC
SECOND RING 2 SECONDS
Tcdh
/CD Tdoc FSKDATA DATA Tsup PCTRL0
PCTRL1
Fig. 17 Relationship between R5 Bit 3 to Bit 4 and RA Bit 1 to Bit 2
34 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
The controller is a CMOS device designed to support the Caller Number Deliver feature which is offered by the Regional Bell Operating Companies. The FSK block comprises one path: the signal path. The signal path consist of an input differential buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect circuit. In a typical application, user can use his own external ring detect output as a triggering input to IO port. User can use this signal to wake up the chip by external ring detect signal. Setting "0, 1" to R5 B4 and B3 (PCTRL1 & PCTRL0) of the RA register activates the FSK decoder block. If B4 and B3 of register R5 is set to "0, 1", the FSK decoder block will be powered down. The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post filter. The output data is then made available at Bit 2 (FSKData) of register RA. This data, as sent by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which precedes the date, time and calling number. If no data is present, the Bit 2 (Data) of register RA is held at "1" state. This is accomplished by a carrier detect circuit which determines if the in-band energy is high enough. If the incoming signal is valid, Bit 1 (/CD) of register RA will be "0" otherwise it will be held at "1". Thus the demodulated data is transferred to Bit 2 (Data) of register RA. If it is not, then the FSK demodulator is blocked. Bit 3 (ROMRI) : External Data ROM read data address auto_increase enable.
RO_IDEN 0 1 1 ROMRI Result Regardless Read/Write external Data ROM, Address flag cannot increase or decrease. Address flag will auto_increase or decrease after a Read/Write of the external Data ROM. Address flag will auto_increase or decrease after a Write to the external Data ROM, but the address flag is constant after reading the external Data ROM.
x
0 1
Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits User can choose different frequency for the main clock by CLK1 and CLK2. All the clock selection is listed below.
PLLEN 1 1 1 1 0 0 0 0 CLK1 0 0 1 1 Don't care Don't care Don't care Don't care CLK0 0 1 0 1 don't care don't care don't care don't care Sub Clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz Main Clock CPU Clock 5.374MHz 5.374MHz (Normal mode) 1.7913MHz 1.7913MHz (Normal mode) 10.7479MHz 10.7479MHz (Normal mode) 3.5826MHz 3.5826MHz (Normal mode) Don't care 32.768kHz (Green mode) Don't care 32.768kHz (Green mode) Don't care 32.768kHz (Green mode) Don't care 32.768kHz (Green mode)
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
35
EM78815 8-Bit Microcontroller Bit 6 (PLLEN) : PLL enable control bit It is CPU mode control register. If PLL is enabled, the CPU will operate in normal mode (high frequency, main clock), otherwise it will run in green mode (low frequency, 32768 Hz). 0/1 disable/enable
3.5826 MHz to analog circuit
PLL Sub-clock 32.768kHz
/ 2 =>1.7913MHz x 1 =>3.5826MHz x 1.5 => 5.374MHz x 3 =>10.7479MHz
1 switch 0 System clock
ENPLL CLK1 ~ CLK0
Fig. 18 Relationship between 32.768kHz and PLL
Bit 7: Unused Register. Always keep this bit to 0, otherwise some un-expected error will occur.
Wake-up Signal Sleep Mode RA (7, 6) = (0, 0) + SLEP TCC time out IOCF Bit 0=1 And "ENI" Counter 1 time out IOCF Bit 1=1 And "ENI" Counter 2 time out IOCF Bit 2=1 And "ENI" WDT time out Port 7 Any one bit in IOCE Page 0 = 1 And "ENI" DED interrupt IOCE page1 bit 6 = 1 And RF Bit 3 logic level variation (switch by EDGE bit) And "ENI" No function Green Mode RA (7, 6) = (x, 0) no SLEP Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) RESET and Jump to Address 0 Interrupt (jump to Address 8 at Page 0) Normal Mode RA (7, 6) = (x, 1) no SLEP Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) Interrupt (jump to address 8 at Page 0) RESET and Jump to Address 0 Interrupt (jump to Address 8 at Page 0)
No function
No function RESET and Jump to Address 0 RESET and Jump to Address 0
No function
Interrupt (jump to Address 8 at Page 0)
Interrupt (jump to Address 8 at Page 0)
36 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
NOTE Port 70 ~ Port 76's wake-up function is controlled by IOCE Page 0 Bit 0~Bit 6 and ENI instruction. They are falling edge trigger. Port 77's wake-up function is controlled by IOCE Page 0 Bit 7. It can be triggered by a falling edge or rising edge (controlled by CONT register).
7.2.16.2 Page 1 Undefined Register: This register is not for use. 7.2.16.3 Page 2 Comparator Control Register
Bit 7 CMPEN R/W-0 Bit 6 CMPREF R/W-0 Bit 5 CMPS1 R/W-0 Bit 4 CMPS0 R/W-0 Bit 3 CMPB3 R/W-0 Bit 2 CMPB2 R/W-0 Bit 1 CMPB1 R/W-0 Bit 0 CMPB0 R/W-0
If user defines Port 63, Port 64 or Port 65 (by ADCS1, ADCS2, ADCS3 at R9 Page 2) as a comparator input or Port 6, then user can use this register to control the comparator's function. Bit 0~Bit 3(CMPB0 ~ CMPB3) : Reference voltage selection of the internal bias circuit for the comparator. Reference voltage for comparator = VDD x (N + 0.5) / 16, N = 0 to 15 Bit 4~Bit 5(CMPS0~CMPS1) : Channel selection from CMP1 to CMP3 for comparator
CMPS1 0 0 1 1 CMPS0 0 1 0 1 Input CMP1 CMP2 CMP3 Reserved
Bit 6(CMPREF) : Switch for comparator reference voltage type 0 internal reference voltage 1 external reference voltage Bit 7(CMPEN) : Enable control bit of comparator. 0/1 disable/enable, when CMPEN bit is set to "0" , the 2.0V ref circuit will be powered off. The relationship between these registers is shown in Fig.19.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
37
EM78815 8-Bit Microcontroller
P65/CMP1
CM P1 MUX PORT65
ADCS1 P66/CMP2 MUX CMP2 MUX PORT66 ADCS2 P67/CMP3 CMP3 MUX PORT67 2 CMPS1 CMPS0 1 0 MUX
+
CMPFLAG
ADCS3 VDD V2_0 ref. MUX 2.0V VR
CMPREF CMPEN 1/2R 1111 R 1110 R MUX
CMPEN VRSEL
0000 1/2R 4 CMPB3 to CM PB0
Fig. 19 Comparator Circuit
CMPEN CMP1 to CMP3 Reference Voltage Set-up time 10us CPU Clock
CMPFLAG
Compare Start
Compare End
Fig. 20 Comparator Timing
38 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.2.16.4 Page 3 Tone 1 Control Register
Bit 7 T17 R/W-0 Bit 6 T16 R/W-0 Bit 5 T15 R/W-0 Bit 4 T14 R/W-0 Bit 3 T13 R/W-0 Bit 2 T12 R/W-0 Bit 1 T11 R/W-0 Bit 0 T10 R/W-0
Bit 0~Bit 7 (T10~T17) : Tone Generator 1 frequency divider and power control. Run in Normal mode. Clock source = 85300Hz T17~T10 = `11111111' Tone Generator 1 will has 334 (85300/255) Hz Sine wave output. : T17~T10 = `00000010' Tone Generator 1 will has 41150(85300/2) Hz Sine wave output. T17~T10 = `00000001' DC bias voltage output T17~T10 = `00000000' Power off Built-in tone generator can generate dialing tone signals for dialing tone type telephones or just a single tone. In DTMF application, there are two kinds of tones, One is the row frequency group (Tone 1), the other is the column frequency group (Tone 2). Each group has four kinds of frequency, user can get a total of 16 kinds of DTMF frequency. A Tone generator contains a row frequency sine wave generator for generating the DTMF signal which is selected by RA Page 3 and a column frequency sine wave generator for generating the DTMF signal which is selected by RB Page 3. This block can generate a single tone by filling one of these two registers. If all the values are low, the power of the tone generators will be turned off.
Tone 2 (RB Page 3) High Group Freq. 1201.4Hz 1332.8Hz 1470.7Hz 1640.4Hz (0X47) (0X40) (0X3A) (0X34) 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D
Tone 1 (RA page3) Low group freq.
699.2Hz (0x07A) 768.5Hz (0x06F) 853.0Hz (0x064) 937.4Hz (0x05B)
Tone 1 and Tone 2 are asynchronous tone generators and both can be used to generate Caller ID FSK signal. In FSK generator application, Tone 1 or Tone 2 can generate 1200Hz Mark bit and 2200Hz Space bit for Bell202 or 1300Hz Mark bit and 2100Hz Space bit for V.23. See the following table.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
39
EM78815 8-Bit Microcontroller
Tone 1 (IOCC Page 1) or Tone 2 (IOCD Page 1) 0x47 0x27 0x42 0x29
Freq. (Hz) 1201.4 2187.2 1292.4 2080.5
Description Bell202 FSK Mark bit Bell202 FSK Space bit V.23 FSK Mark bit V.23 FSK Space bit
The Tone generator can also generate CW or SMS signal. See the following table.
Tone 1 (IOCC Page 1) or Tone 2 (IOCD Page 1) 0x28 0x1F Freq. (Hz) 2132.5 2751.6 Description CAS freq CAS freq
7.2.17 RB Port B I/O Data, Key Strobe, Tone 2 Generator
7.2.17.1 Page 0 Port B I/O Data
Bit 7 PB7 R/W-X Bit 6 PB6 R/W-X Bit 5 PB5 R/W-X Bit 4 PB4 R/W-X Bit 3 PB3 R/W-X Bit 2 PB2 R/W-X Bit 1 PB1 R/W-X Bit 0 PB0 R/W-X
Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit Port B ( 0~7 ) I/O data register. User can use the IOC register to define each bit as either input or output. 7.2.17.2 Page 1 Undefined Register: This register is not for use. 7.2.17.3 Page 2 Key Strobe Control Register
Bit 7 STRB7 R Bit 6 STRB6 R Bit 5 STRB5 R Bit 4 STRB4 R Bit 3 STRB3 R Bit 2 STRB2 R Bit 1 STRB1 R Bit 0 STRB0 R
Bit 0 ~ Bit 7 (STRB0 ~ STRB7) : Key strobe control bits. These key strobe control registers correspond to Port 80 ~ Port 87. Refer to Keystobe explanation (RE Page 3). 7.2.17.4 Page 3 Tone 2 Control Register
Bit 7 T27 R/W-0 Bit 6 T26 R/W-0 Bit 5 T25 R/W-0 Bit 4 T24 R/W-0 Bit 3 T23 R/W-0 Bit 2 T22 R/W-0 Bit 1 T21 R/W-0 Bit 0 T20 R/W-0
Bit 0~Bit 7(T20~T27) : Tone Generator 1 frequency divider and power control. Refer to RA Page 3 Tone 1 control register for details.
40 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.2.18 RC Port C I/O Data, Data RAM Data Buffer, Tone 2 Generator
7.2.18.1 Page 0 Port C I/O Data
Bit 7 PC7 R/W-X Bit 6 PC6 R/W-X Bit 5 PC5 R/W-X Bit 4 PC4 R/W-X Bit 3 PC3 R/W-X Bit 2 PC2 R/W-X Bit 1 PC1 R/W-X Bit 0 PC0 R/W-X
Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit Port C ( 0~7 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.18.2 Page 1 Data RAM Data Buffer 1
Bit 7 RAM1D7 R/W-X Bit 6 RAM1D6 R/W-X Bit 5 RAM1D5 R/W-X Bit 4 RAM1D4 R/W-X Bit 3 RAM1D3 R/W-X Bit 2 RAM1D2 R/W-X Bit 1 RAM1D1 R/W-X Bit 0 RAM1D0 R/W-X
Bit 0 ~ Bit 7 (RAM1D0 ~ RAM1D7) : Data RAM data Buffer 1 for RAM reading or writing. Example. MOV MOV MOV MOV MOV MOV A,@1 RD_PAGE1,A A,@0 RE_PAGE1,A A,@0x55 RC_PAGE1,A ;write data 0x55 to DATA RAM ;which is address "0001" ;read data
MOV :
A,RC_PAGE1
7.2.18.3 Page 2 Key Strobe Control Register
Bit 7 STRB15 R Bit 6 STRB14 R Bit 5 STRB13 R Bit 4 STRB12 R Bit 3 STRB11 R Bit 2 STRB10 R Bit 1 STRB9 R Bit 0 STRB8 R
Bit 0 ~ Bit 7 (STRB8 ~ STRB15) : Key strobe control bits These key strobe control registers correspond to Port 90 ~ Port 97. Refer to Key stobe explanation (RE Page 3). 7.2.18.4 Page 3 Undefined Register: This register is unimplemented, not for use.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
41
EM78815 8-Bit Microcontroller
7.2.19 RD Port D I/O Data, Data RAM Address
7.2.19.1 Page 0 Port D I/O Data, Data RAM Address
Bit 7 PD7 R/W-X Bit 6 PD6 R/W-X Bit 5 PD5 R/W-X Bit 4 PD4 R/W-X Bit 3 PD3 R/W-X Bit 2 PD2 R/W-X Bit 1 PD1 R/W-X Bit 0 PD0 R/W-X
Bit 0 ~ Bit 7 (PD0 ~ PD7) : 7-bit Port D ( 0~6 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.19.2 Page 1 Data RAM Address 1 (Low 8 bits)
Bit 7 RAM1A7 R/W-X Bit 6 RAM1A6 R/W-X Bit 5 RAM1A5 R/W-X Bit 4 RAM1A4 R/W-X Bit 3 RAM1A3 R/W-X Bit 2 RAM1A2 R/W-X Bit 1 RAM1A1 R/W-X Bit 0 RAM1A0 R/W-X
Bit 0~Bit 7 (RAM1A0 ~ RAM1A7) : Data RAM address1 (Address 0 to Address 7) for RAM reading or writing 7.2.19.3 Page 2 Undefined Register 7.2.19.4 Page 3 Undefined Register These two register are unimplemented, not for use.
7.2.20 RE Interrupt Flag 1, Data RAM Address 1 (H) CAS, Key Scan
7.2.20.1 Page 0 Interrupt Flag 1
Bit 7 INT7 R/W-0 Bit 6 INT6 R/W-0 Bit 5 INT5 R/W-0 Bit 4 INT4 R/W-0 Bit 3 INT3 R/W-0 Bit 2 INT2 R/W-0 Bit 1 INT1 R/W-0 Bit 0 INT0 R/W-0
Interrupt flag registers. User can only clear these bits from 1 to 0 but cannot set them from 0 to 1. Bit 0 (INT0) : External INT0 pin interrupt flag If Port 70 has a falling edge trigger signal, the CPU will set this bit. Bit 1 (INT1) : External INT1 pin interrupt flag If Port 71 has a falling edge trigger signal, the CPU will set this bit. Bit 2 (INT2) : External INT2 pin interrupt flag If Port 72 has a falling edge trigger signal, the CPU will set this bit. Bit 3 (INT3) : External INT3 pin interrupt flag If Port 73 has a falling edge trigger signal, the CPU will set this bit. Bit 4 (INT4) : External INT4 pin interrupt flag If Port 74 has a falling edge trigger signal, the CPU will set this bit. Bit 5 (INT5) : External INT5 pin interrupt flag If Port 75 has a falling edge trigger signal, the CPU will set this bit.
42 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 6 (INT6) : External INT6 pin interrupt flag If Port 76 has a falling edge trigger signal, the CPU will set this bit. Bit 7 (INT7) : External INT7 pin interrupt flag If Port 77 has a falling (or rising and falling) edge trigger signal, the CPU will set this bit.
Signal INT0 : INT6 INT7 Trigger Falling edge Falling/Falling & Rising Edge Controlled by CONT register Remark
7.2.20.2 Page 1 Data RAM Address 1(H)
Bit 7 - x Bit 6 - x Bit 5 - x Bit 4 - x Bit 3 Bit 2 Bit 1 Bit 0 RAM1A8 R/W-X
RAM1A11 RAM1A10 RAM1A9 R/W-X R/W-X R/W-X
Bit 0~Bit 3 (RAM1A8 ~ RAM1A11) : Data RAM address (Address 8 to Address 11) for RAM reading. Bit 4~Bit 7 Undefined Register. These registers are not certain whether 0 or 1. Do not use these registers.
7.2.20.3 Page 2 CAS Detected Flag, Keyscan
Bit 7 CAS R Bit 6 - x Bit 5 Key strobe R/W-0 Bit 4 Keyscan R/W-0 Bit 3 LCD1 R/W-0 Bit 2 LCD0 R/W-0 Bit 1 - x Bit 0 - x
Bit 0~Bit 1 : Undefined register. These bits are unimplemented, not for use. Bit 2~Bit 3 (LCD0~LCD1) : These two bits are used to enable/disable key scan and the LCD controller.
LCD1 0 0 1 1 LCD0 0 1 0 1 Sates Keyscan disable (ignore Keyscan bit) External LCD controller disable Keyscan disable (ignore Keyscan bit) External LCD controller disable Keyscan disable (ignore Keyscan bit) External LCD controller disable Keyscan enable (Keyscan bit must = 1) External LCD controller enable
Bit 4 (Keyscan) : Key scan function enable control bit. 0/1 disable/enable If Keyscan function is enabled (LCD0, LCD1 and Keyscan =1), Port 8 and Port 9 will be pulled high automatically and become key strobe pins.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
43
EM78815 8-Bit Microcontroller
The key scan waveform is as follows.
K ey scan pi n(P8,P9)
V DD
30us
GN D
Fig.21 Keyscan Waveform
Bit 5 (KEYSTRB) : Key strobe enable control bit 0/1 disable/enable Key strobe signal , if you set this bit , the segment will switch to strobe signal temporally and output a zero signal ( one instruction long ) one by one from Port 80 to Port 87 and Port 90 to Port 97. During one strobe time, the CPU will check whether Port 7 (0:3) is equal to "1111" or not. If not, the CPU will latch a zero at RB Page 1 and RC Page 1 one by one depending on which segment strobe. After strobe, this bit will be cleared. Fig. 22 is a key strobe signal.
One instruction
REGISTER RB(0) RB(1) RB(2) RB(3) RB(4) RB(5) RB(6) RB(7) RC(0) RC(1) RC(2) RC(3) RC(4) RC(5) RC(6) RC(7)
STROBE PORT80 PORT81 PORT82 PORT83 PORT84 PORT85 PORT86 PORT87 PORT90 PORT91 PORT92 PORT93 PORT94 PORT95 PORT96 PORT97
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Fig.22 Key strobe Signal
44 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Bit 6 Unused The following figure shows the relationship between Keyscan, and Key strobe. Fig.24 is a Keyscan flow by interrupt trigger.
Relationship Between Port 8, Port 9, Keyscan, Keystrobe
Keyscan Pulse
Keyscan Control 0 MUX 1 Key strobe
Fig. 23 Keyscan, Key strobe and Segments
Port 8, Port 9 Key strobe Signal
Set Port 7(3:0) input Port 7 pull high Enable Keyscan signal Set INT0~INT3 interrupt ENI
N Interrupt occur?
Y Enable main clock (Normal mode) Program delay Analysis external interrupt (column key ) Set strobe function Enable Key strobe Program delay Read strobe data (row key)
Execution Key function
Get the Key location
Fig. 24 Key Scan Flow By Interrupt Trigger Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
45
EM78815 8-Bit Microcontroller
Bit 7 (CAS) : Call Waiting decoding output 0/1 CW data valid / No data 7.2.20.4 Page 3 UART transmitter data buffer
Bit 7 URT7 R/W-X Bit 6 URT6 R/W-X Bit 5 URT5 R/W-X Bit 4 URT4 R/W-X Bit 3 URT3 R/W-X Bit 2 URT2 R/W-X Bit 1 URT1 R/W-X Bit 0 URT0 R/W-X
Bit 0~Bit 7(URT0~URT7) : Low 8-bit UART transmitter data buffer
7.2.21 RF Interrupt flag
Bit 7 RBF/STD R/W-0 Bit 6 FSK/CW R/W-0 Bit 5 - x Bit 4 UART R/W-0 Bit 3 DED R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCC R/W-0
Note: "1" means interrupt request "0" means non-interrupt
Bit 0 (TCC) :
TCC timer overflow interrupt flag Set when TCC timer overflows.
Bit 1 (CNT1) : Counter 1 timer overflow interrupt flag Set when Counter 1 timer overflows. Bit 2 (CNT2) : Counter 2 timer overflow interrupt flag Set when Counter 2 timer overflows. Bit 3 (DED) : Differential Energy Detector (DED) Interrupt flag output data. If DEDD (RE Page 2 Bit 7) has a falling edge signal (or falling & rising edge signal, switch by IOCE Page 1 Bit 5), the CPU will set this bit. Bit 4 (UART) : Universal Asynchronous Receiver Transmitter interrupt flag. When the transmitter buffer is empty, receiver buffer full or receiver data error, this bit will be set. Bit 5: Undefined register. These bits are unimplemented, not for use.
Bit 6 (FSK/CW) : FSK data or Call waiting data interrupt flag. If FSKDATA or CAS has a falling edge trigger signal, the CPU will set this bit. Bit 7 ( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt If serial IO's RBF signal has a rising edge signal (RBF set to "1" when data is transferred completely), the CPU will set this bit. Or when the DTMF receiver's STD signal has a rising edge signal (the DTMF decodes a DTMF signal). IOCF is the interrupt mask register. User can read and clear.
46 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Trigger edge is shown in the following table:
Signal TCC Counter 1 Counter 2 DED UART FSK RBF/STD Trigger Time out Time out Time out Signal detect Receiver full, Transmitter empty or error (if enabled) Falling edge Rising edge 8/16 bits select by CONT register Remark
EM78815 MCU will store ACC, R3 status and R5 Page automatically after an interrupt is triggered. It will be restored after instruction "RETI". 7.2.21.1 Page 1 External Data ROM
Bit 7 EXA8 R/W-0 Bit 6 EXA7 R/W-0 Bit 5 EXA6 R/W-0 Bit 4 EXA5 R/W-0 Bit 3 EXA4 R/W-0 Bit 2 EXA3 R/W-0 Bit 1 EXA2 R/W-0 Bit 0 EXA1 R/W-0
Bit 0~Bit 7(EXA1~EXA8) : Expanding Data ROM start address A1~A8 7.2.21.2 Page 2 External Data ROM
Bit 7 EXA16 R/W-0 Bit 6 EXA15 R/W-0 Bit 5 EXA14 R/W-0 Bit 4 EXA13 R/W-0 Bit 3 EXA12 R/W-0 Bit 2 EXA11 R/W-0 Bit 1 EXA10 R/W-0 Bit 0 EXA9 R/W-0
Bit 0~Bit 7(EXA9~EXA16) : Expanding Data ROM start address A9~A16,,IOCB Page 1 Bit 7 is the MSB (EXA17) for Expanding Data ROM start address. 7.2.21.3 Page 3 Unused
7.2.22 R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers
7.3 Special Purpose Registers
7.3.1 A (Accumulator)
Internal data transfer, or instruction operand holding It's not an addressable register.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
47
EM78815 8-Bit Microcontroller
7.3.2 CONT (Control Register)
Bit 7 INT/EDGE Bit 6 INT Bit 5 TS Bit 4 DAEN Bit 3 PAB Bit 2 RSR2 Bit 1 RSR1 Bit 0 RSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 3 (PAB) :
Prescaler assigned bit 0/1 TCC/WDT
Bit 4 (DAEN) :
Current DA enable control 0/1 disable/enable
Bit 5 (TS) :
TCC signal source Instruction clock / 16.384kHz Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See Fig.15.
Bit 6 (INT) :
INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions
Bit 7(INT_EDGE) : interrupt edge type of P77 0 P77 's interrupt source is a rising and falling edge signal. 1 P77 's interrupt source is a falling edge signal. The CONT register is readable (CONTR) and writable (CONTW). There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8-bit counter is available for TCC or WDT determined by the status of Bit 3 (PAB) of the CONT register. See the prescaler ratio in the CONT register. Fig. 25 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions, when in WDT mode. The prescaler will not be cleared by SLEP instructions, when in TCC mode.
48 * Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Data Bus
Instruction clock 16.384kHz
M U X
M U X
PAB
SYNC 2 cycles
TCC(R1)
TS
TCC overflow interrupt
W DT
WDTE
M U X
PAB
8-bit Counter
PSR0 ~ PSR2
8-to-1 MUX
MUX
PAB
WDT timeout
Fig. 25 Block Diagram of TCC and WDT
7.3.3 IOC5 Address Automatic Increase/Decrease Control, Data RAM Data Buffer 2
7.3.3.1 Page 0 Address Automatic Increase/Decrease control register
Bit 7 DA2_ID R/W-1 Bit 6 DA1_ID R/W-1 Bit 5 DO_ID R/W-1 Bit 4 - x Bit 3 Bit 2 Bit 1 Bit 0 - x DA2_IDEN DA1_IDEN DO_IDEN R/W-0 R/W-0 R/W-0
Bit 0 :
Undefined register, not for use
Bit 1 (DO_IDEN) : Enable Data ROM address flag Increase/Decrease Enable Function. If this bit is set, the Data ROM address will increase or decrease after accessing (read or write) the Data ROM. When Expanded Data ROM is used, user can read or write into the external memory. By controlling RA Page 0 Bit 3, address auto increase/decrease function can be changed. Refer to RA Page 0 for detailed description. 1/0 Enable / Disable Bit 2 (DA1_IDEN) : Enable Data RAM address Flag 1 (RD and RE register) Increase/Decrease Enable Function. If this bit is set, the Data RAM address will increase or decrease after accessing (read or write) the Data RAM (RC register). 1/0 Enable / Disable
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
49
EM78815 8-Bit Microcontroller
Bit 3 (DA2_IDEN) : Enable Data RAM Address Flag 2 (IOC6 and IOC7) Increase/Decrease Enable Function. If this bit is set, the Data RAM address will increase or decrease after accessing (read or write) the Data RAM (IOC5 register). 1/0 Enable / Disable Bit 4 : Bit 5 (DO_ID) : Undefined register, not for use. Data ROM address automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 auto increase / auto decrease Bit 6 (DA1_ID) : Data RAM address (RD and RE register) automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 auto increase / auto decrease Bit 7 (DA2_ID) : Data RAM address (IOC6 and IOC7 register) automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 auto increase / auto decrease 7.3.3.2 Page 1 Data RAM Data Buffer 2
Bit 7 RAM2D7 R/W-X Bit 6 RAM2D6 R/W-X Bit 5 RAM2D5 R/W-X Bit 4 RAM2D4 R/W-X Bit 3 RAM2D3 R/W-X Bit 2 RAM2D2 R/W-X Bit 1 RAM2D1 R/W-X Bit 0 RAM2D0 R/W-X
Bit 0 ~ Bit 7 (RAM1D0 ~ RAM1D7) : Data RAM buffer for RAM reading or writing. Location RC~RE Page 2, user can move a large number of continuous data from an address to another into the data RAM. Example (move data from 0x0000 to 0x1000): BC MOV IOW BS BS BC MOV MOV MOV R3,@5 A , @0xF0 0x05 R3 , @5 R3 , @6 R3 , @7 A , @0x00 0x0D , A 0x0E , A
;Enable Data RAM Flag 1 and Flag 2 ;auto_increase function :Set corresponding page
;Assign Data RAM Index 1 ;start address "0x0000"
50 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
IOW MOV IOW MOV IOW MOV IOW : :
0x06 A , @0x10 0x07 A , 0x0C 0x05 A , 0x0C 0x05
; Assign DATA RAM Index 2 start ; address "0x1000"
;Read data from Index 1(address:0x0000) ;Write data to Index 2(address:0x1000) ;Read data from Index 1(address:0x0001) ;Write data to Index 2(address:0x1001)
7.3.4 IOC6 Port 6 I/O Control, Data RAM Address (L)
7.3.4.1 Page 0 Port 6 I/O Control
Bit 7 IOC67 R/W-1 Bit 6 IOC66 R/W-1 Bit 5 IOC65 R/W-1 Bit 4 IOC64 R/W-1 Bit 3 IOC63 R/W-1 Bit 2 IOC62 R/W-1 Bit 1 IOC61 R/W-1 Bit 0 IOC60 R/W-1
Bit 0~Bit 7 (IOC60 ~ IOC67) : Port 6 (0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 7.3.4.2 Page 1 Data RAM Address 2 (L)
Bit 7 RAM2A7 R/W-X Bit 6 RAM2A6 R/W-X Bit 5 RAM2A5 R/W-X Bit 4 RAM2A4 R/W-X Bit 3 RAM2A3 R/W-X Bit 2 RAM2A2 R/W-X Bit 1 RAM2A1 R/W-X Bit 0 RAM2A0 R/W-X
Bit 0~Bit 7 (RAM2A0 ~ RAM2A7) : Data RAM address (Address 0 to Address 7) for RAM reading or writing
7.3.5 IOC7 PORT 7 I/O Control, Data RAM Address 2 (H)
7.3.5.1 Page 0 Port 7 I/O Control
Bit 7 IOC77 R/W-1 Bit 6 IOC76 R/W-1 Bit 5 IOC75 R/W-1 Bit 4 IOC74 R/W-1 Bit 3 IOC73 R/W-1 Bit 2 IOC72 R/W-1 Bit 1 IOC71 R/W-1 Bit 0 IOC70 R/W-1
Bit 0~Bit 7 (IOC70 ~ IOC77) : Port 7(0~7) I/O direction control register 0 relative I/O pin as output 1 relative I/O pin into high impedance 7.3.5.2 Page 1 Data RAM Address 2 (H)
Bit 7 - x Bit 6 - x Bit 5 - x Bit 4 - x Bit 3 R/W-X Bit 2 R/W-X Bit 1 R/W-X Bit 0 RAM2A8 R/W-X RAM2A11 RAM2A10 RAM2A9
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
51
EM78815 8-Bit Microcontroller Bit 0~Bit 3 (RAM2A8 ~ RAM2A11) : Data RAM address (Address 8 to Address 11) for RAM reading or writing Bit 4~Bit 7 : Undefined register, not for use.
7.3.6 IOC8 Port 8 I/O Control
7.3.6.1 Page 0 Port 8 I/O Control
Bit 7 IOC87 R/W-1 Bit 6 IOC86 R/W-1 Bit 5 IOC85 R/W-1 Bit 4 IOC84 R/W-1 Bit 3 IOC83 R/W-1 Bit 2 IOC82 R/W-1 Bit 1 IOC81 R/W-1 Bit 0 IOC80 R/W-1
Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : Port 8 (0~7) I/O direction control register 0 puts the relative I/O pin as output 1 puts the relative I/O pin into high impedance 7.3.6.2 Page 1 Undefined register This register is unimplemented, not for use.
7.3.7 IOC9 Port 9 I/O Control
7.3.7.1 Page 0 Port 9 I/O Control
Bit 7 IOC97 R/W-1 Bit 6 IOC96 R/W-1 Bit 5 IOC95 R/W-1 Bit 4 IOC94 R/W-1 Bit 3 IOC93 R/W-1 Bit 2 IOC92 R/W-1 Bit 1 IOC91 R/W-1 Bit 0 IOC90 R/W-1
Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : Port 9 (0~7) I/O direction control register 0 puts the relative I/O pin as output 1 puts the relative I/O pin into high impedance 7.3.7.2 Page 1 Undefined register This register is unimplemented, not for use.
7.3.8 IOCA Undefined Register
IOCA Page 0 and Page 1 are unimplemented, not for use.
52 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.3.9 IOCB Port B I/O Control, External LCD Driver Interface (for EMC 65x132)
7.3.9.1 Page 0 Port B I/O Control
Bit 7 IOCB7 R/W-1 Bit 6 IOCB6 R/W-1 Bit 5 IOCB5 R/W-1 Bit 4 IOCB4 R/W-1 Bit 3 IOCB3 R/W-1 Bit 2 IOCB2 R/W-1 Bit 1 IOCB1 R/W-1 Bit 0 IOCB0 R/W-1
Bit 0~Bit 7 (IOCB0~IOCB7) : Port B(0~7) I/O direction control register 0 puts the relative I/O pin as output 1 puts the relative I/O pin into high impedance 7.3.9.2 Page 1 External LCD Driver Controller
Bit 7 EXA17 R/W-0 Bit 6 CWPWR R/W-0 Bit 5 x x Bit 4 x x Bit 3 CSS R/W-0 Bit 2 CSSON R/W-0 Bit 1 DIS R/W-0 Bit 0 EXLCD R/W-0
Bit 0(EXLCD) : External LCD driver enable/disable 0/1 Port B, Port C normal IO/External LCD driver control (RE Page 2 LCD0, LCD1 = 1) If EXLCD is equal to 0, Port B and Port C output are normal IO. When EXLCD is equal to 1, Port B and Port C are switch to external LCD driver control pin. At this time, when user executes a read or write Port B instruction, Port C timing characteristic is shown below:
Tah
A0(PC4) CS (PC0/PC1)
Taw
WR(PC2)/ RD(PC3) Port B Port B
Tcyc Tcc Tdh Tds
Data
Toh
Tacc
Data
Fig. 26 Timing Characteristics of the External LCD Driver Data Read/Write
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
53
EM78815 8-Bit Microcontroller
Symbol Tah Taw Tcyc Tcc Tds Tdh Tacc Toh
Applicable Pins A0 A0 A0 WR/RD D0 ~D7 D0 ~D7 D0 ~D7 D0 ~D7 0 0 150 60 20 10 10
Rated Value Min. Max. 60 40
Unit
ns
Tah : Address hold time Taw : Address set-up time Tcyc : System cycle time Tcc : Pulse width Tds : Data set-up time Tdh : Data hold time Tacc : Read access time Toh : Output disable time User can operate in coordination with the on-chip Data ROM address automatic increase function to write a large number of data from the internal Data ROM to the external LCD RAM. Example ( To collocate EM9L8580 LCD driver ): START: MOV IOW MOV IOW MOV MOV MOV MOV MOV
MOV
A , @0x0C; IOC5_PAGE0 A , @0x09 IOCB_PAGE1 A , @0xB0; RB_PAGE0 , A A , @0x10 RB_PAGE0 , A A , @0x00
RB_PAGE0 , A ; Set external LCD driver start address Column 0
;Set Data ROM address automatic increase ;after read/write data
;External LCD driver Chip 1 Instruction mode ;select
;Set external LCD driver start address Page 0
MOV
54 *
A , @0x00;
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
MOV MOV MOV MOV IOW CN1: MOV MOV JMP
R7_PAGE1 , A; R8_PAGE1 , A; R9_PAGE1 , A A , @0x0B IOCB_PAGE1 ;select data mode ;Start address: 0x00000
A , R6_PAGE1 RB_RAGE0 , A LOOP
;read data from Data ROM and address flag ;increase ;write data to external LCD driver
Bit 1 (DIS) :
External LCD driver Data/Instruction switch 0/1 Instruction/Data When EXLCD is equal to 1 and DIS bit equal to 0, the MCU will transmit/receive instruction. A0 (Port C7) will output a "0". If the DIS bit is set to 1, the MCU will transmit/receive data. A0 (Port C4) will output a "1".
Bit 2 (CSSON) : External LCD driver select enable
CSSON 0 1 1 CSS0 x 0 1 CS1..CS2 Low - CS1 CS2 High CS1, CS2 CS2 CS1
Example for EMC 65x132 LCD driver : MOV IOW MOV MOV MOV MOV MOV MOV MOV IOW MOV MOV : A, @0x01 IOCB_PAGE1 A,@0xB0 RB,A A,@0x10 RB,A A,@0x00 RB,A A,@0x03 IOCB_PAGE1 A,@0xFF RB,A ;Write 0xFF to COM0 &SEG0 ;Switch to DATA mode ;Select external LCD driver SEG Lower 4 bit = 0 ;Select external LCD driver SEG Upper 4 bit = 0 ;Select external LCD driver COM0 ;Select external LCD driver & Instruction ;mode
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
55
EM78815 8-Bit Microcontroller
User must assign an external LCD address for the first time. After writing or reading the display data, the Segment address is automatically incremented. Hence, the MCU can continuously write or read data to the address. Bit 3 (CSS) : External LCD driver chip select bit 0/1 Chip 1 / Chip 2 Bit 4 ~ Bit 5 : Unused
Bit 6(CWPWR) : CAS Decoder Power Control 0/1 Power off / Power on Bit 7 (EXA17) : Expanded Data ROM start address MSB. This bit can be set only at the connected pin "EXSAL" to VDD.
7.3.10 IOCC Port C I/O Control, Port 6 Pull-high Register
7.3.10.1 Page 0 Port C I/O Control
Bit 7 IOCC7 R/W-1 Bit 6 IOCC6 R/W-1 Bit 5 IOCC5 R/W-1 Bit 4 IOCC4 R/W-1 Bit 3 IOCC3 R/W-1 Bit 2 IOCC2 R/W-1 Bit 1 IOCC1 R/W-1 Bit 0 IOCC0 R/W-1
Bit 0~Bit 7 (IOCC0~IOCC7) : Port C (0~7) I/O direction control register 0 puts the relative I/O pin as output 1 puts the relative I/O pin into high impedance 7.3.10.2 Page 1 Port 6 Pull-high Register
Bit 7 PH67 R/W-0 Bit 6 PH66 R/W-0 Bit 5 PH65 R/W-0 Bit 4 PH64 R/W-0 Bit 3 PH63 R/W-0 Bit 2 PH62 R/W-0 Bit 1 PH61 R/W-0 Bit 0 PH60 R/W-0
Bit 0~Bit 7(PH60~PH67) : PORT6(0~7) pull high control register 0 disable pull-high function 1 enable pull-high function
7.3.11 IOCD Port D I/O Control, Port 7 Pull-high Register
7.3.11.1 Page 0 Port D I/O Control
Bit 7 IOCD7 R/W-1 Bit 6 IOCD6 R/W-1 Bit 5 IOCD5 R/W-1 Bit 4 IOCD4 R/W-1 Bit 3 IOCD3 R/W-1 Bit 2 IOCD2 R/W-1 Bit 1 IOCD1 R/W-1 Bit 0 IOCD0 R/W-1
Bit 0~Bit 6 (IOCD0~IOCD6) : Port D (0~6) I/O direction control register 0 puts the relative I/O pin as output 1 puts the relative I/O pin into high impedance
56 * Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.3.11.2 Page 1 Port 7 Pull High Register
Bit 7 PH77 R/W-0 Bit 6 PH76 R/W-0 Bit 5 PH75 R/W-0 Bit 4 PH74 R/W-0 Bit 3 PH73 R/W-0 Bit 2 PH72 R/W-0 Bit 1 PH71 R/W-0 Bit 0 PH70 R/W-0
Bit 0~Bit 7(PH70~PH77) : Port 7(0~7) pull high control register 0 disable pull-high function 1 enable pull-high function
7.3.12 IOCE Interrupt Mask, Differential Energy Detect
7.3.12.1 Page 0 Interrupt Mask Register 1
Bit 7 INT7 R/W-0 Bit 6 INT6 R/W-0 Bit 5 INT5 R/W-0 Bit 4 INT4 R/W-0 Bit 3 INT3 R/W-0 Bit 2 INT2 R/W-0 Bit 1 INT1 R/W-0 Bit 0 INT0 R/W-0
Bit 0~Bit 7 :
Interrupt enable bits 0/1 disable interrupt/enable interrupt
7.3.12.2 Page 1 Differential Energy Detect
Bit 7 VRSEL R/W-0 Bit 6 DEDD R Bit 5 EDGE R/W-0 Bit 4 WUEDD R/W-0 Bit 3 CW_SMB R/W-0 Bit 2 DEDCLK R/W-0 Bit 1 R/W-0 Bit 0 R/W-0 DEDPWR DEDTHD
Bit 0 (DEDTHD) : Minimum detection threshold for Differential Energy Detector (DED) 0/1 -45dBm/-30dBm Bit 1 (DEDPWR) : Power control of Differential Energy Detector (DED) 0/1 Power off / Power on Bit 2 (DEDCLK) : Operating clock for Differential Energy Detector (DED) 0/1 32.768kHz/3.5826 MHz This bit is used to select operating clock for the Differential Energy Detector (DED). When this bit is set to "1", the PLL is also enabled regardless of RA Bit 6 (ENPLL). During this time, the Energy detector works at high frequency mode. When this bit is set to "0", the Energy Detector works at a low frequency mode. The difference between high frequency and low frequency is as follows.
DEDPWR 0 1 1 1 1 DEDCLK x 0 0 1 1 ENPLL x 0 1 0 1 Energy Detector Clock x 32.768 kHz 32.768 kHz 3.5826 MHz 3.5826 MHz Main CLK Determined by ENPLL Disable Enable Enable Enable
Note: "x" means don't care
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
57
EM78815 8-Bit Microcontroller
Bit 3(CW_SMB) : Call Waiting / short message receiver switch 0 Short message mode select 5.5% CAS tone accepted frequency range deviation. (Protocol: 5%) 1 Call Waiting mode select 2.0% CAS tone accepted frequency range deviation. Bit 4 (WUEDD) : Wake-up control for the Energy Detector (DED) output data 1/0 enable/disable Bit 5 (EDGE) : Wake-up and interrupt trigging edge control of the Energy Detector (DED) output 1/0 Rising edge and Falling edge trigger / Falling edge trigger Bit 6(DEDD) : Output data for Differential Energy Detector (DED). If the input signal from TIP/EGIN1 and RING/EGIN2 pins to Differential Energy Detector is over the threshold level setting at IOCE Page 2 Bit 0 (DEDTHD), the DED will extract the zero-crossing pulse waveform corresponding to the input signal. Reference voltage VR selection bit for Comparator 0 VR = VDD 1 VR = 2.0V When this bit is set to "0", V2_0 reference circuit will be powered off. The 2.0V reference circuit is only powered on when this bit and RA Page 2 bit 7 (CMPEN) are all set to "1".
Bit 7 (VRSEL) :
7.3.13
Bit 7 RBF/STD R/W-0
IOCF Interrupt Mask Register 2
Bit 6 FSK/CW R/W-0 Bit 5 - x Bit 4 UART R/W-0 Bit 3 DED R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCC R/W-0
Bit 0~Bit 7 :
Interrupt enable bits 0/1 Disable interrupt/enable interrupt
58 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.4 I/O Port
PCRD
Q
P R C L
D CLK PCWR
Q
PORT
Q
P R C L
D CLK PDWR
IOD
Q
PDRD 0 1 M U X
Fig. 27 I/O Port and I/O Control Register Circuit
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig. 27.
* The MCU will have a large current consumption when the IO is set to input
and at floating state. Be careful to set unused IO to output or connect them to VDD or GND when they are set to input status.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
59
EM78815 8-Bit Microcontroller
7.5 Reset
The Reset can be caused by: (1) Power-on voltage detector reset (POVD) and power on reset (2) WDT time-out (if enabled and in Green or Normal mode) (3) /Reset pin pull low
NOTE In Case (1), the POVD is controlled by Code Option. If you enable POVD, the CPU will reset at 2V and below, thus, the CPU will consume more current, which is 3A. The power-on reset circuit is always enabled. It will reset the CPU at 1.4V and consume 0.5A.
Once a Reset occurs, the following functions are performed: The oscillator is running, or will be started The Program Counter (R2) is set to all "0" When powered on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared The Watchdog timer and prescaler counter are cleared The Watchdog timer is disabled The CONT register is set to all "1" The other register (Bit 7 ~ Bit 0)
R Register Page 0 xxxx xxxx
00xx xxxx
Address
R Register Page 1
0000 0000
R Register Page 2
0000 0000
R Register Page 3 xxxx xxxx xxxx xxxx xxxx 0000
0000 0000 0000 0000
IOC Register Page 0 --1111 0000 1111 1111 1111 1111 1111 1111 1111 1111
IOC Register Page 1 --xxxx xxxx xxxx xxxx xxxx xxxx
00000000 00000000
1 4 5 6 7 8 9 A B C D E F
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000 0000 0000 0000 0000
x000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
0000 0xx0
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
0000 0000
xxxx 0000
0000 0xxx 0000 0000 1111 1111 1111 1111
xxxx xxxx xxxx x000
0000 0000 0000 0000
xxxx xxxx
1111 1111 1111 1111 1111 1111 0000 0000 0000 0000
xxxx xxxx
00xx 0000 0000 0000 0000 0000 0x00 0000
xxxx xxxx xxxx xxxx xxxx xxxx
0000 0000 00xx 0000
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xx00 xxxx
0000 0000
--
60 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.6 Wake-up
The controller provides a power saving mode: (1) Sleep mode, RA (7) = 0 + "SLEP" instruction The controller will turn off all the CPU and crystal. User has to turn off by software all the other circuits with power control like Keytone control or PLL control (which has an enable register). Wake-up from Sleep mode: (1) WDT time out (2) External interrupt (3) /Reset pull low All these cases will reset the controller, and run the program at address zero. The status is the same as that of the power-on reset.
7.7 Interrupt
RE and RF are the interrupt status registers which record the interrupt request in flag bits. The IOCE and IOCF are the interrupt mask registers. The TCC timer, Counter 1 and Counter 2 are internal interrupt sources. P70 ~ P77 (INT0 ~ INT7) are external interrupt input with external interrupt sources. If the interrupts come from these interrupt sources, then the RE or RF register will generate a '1' flag to the corresponding register if the IOCE or IOCF registers are enabled. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RE and RF registers. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts, to avoid recursive interrupts.
7.8 Instruction Set
Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
61
EM78815 8-Bit Microcontroller
Legend: addr: address b: bit Binary Instruction 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 Hex 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr
i: Table pointer control k: constant
p: special file register (0h~1Fh) r: File Register
Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R
Operation No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2 + A R2 bits 9, 10 do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0)
Status Affected None C None T, P T, P None None None None None None None Z, C, DC None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C
Instruction Cycle 1 1 1 1 1 1 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 if skip 2 if skip 1 1 1 1
0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
0 0110 00rr 0 0110 01rr 0 0110 10rr 0 0110 11rr 62 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Instruction Cycle 1 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1
Binary Instruction 0 0111 00rr 0 0 0 0 0 0 0 0111 0111 0111 100b 101b 110b 111b 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
Hex 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk
Mnemonic SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k
Operation R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC KR5(4:0) k+A A
Status Affected None None None None None None None None None None None Z Z Z None Z, C, DC None None Z, C, DC
1 00kk kkkk kkkk 1 1 1 1 1 1 1 01kk 1000 1001 1010 1011 1100 1101 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk
1 1110 0000 0001 1 1110 1kkk kkkk 1 1111 kkkk kkkk
Note: One instruction cycle = 2 main clock
7.9 Code Option Register
The controller has one Code option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution.
7.9.1 Code Option Register 1 (Program ROM)
Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 /DED Bit 0 /POVD
Bit 0 (/POVD) : Power-on Voltage Detector 0/1 Enable / disable the Voltage Detector
/POVD 1 0 2.2V /POVD Reset Voltage No Yes (2.2V) 2.2V Power-on Reset Voltage Yes (2.2V) No Sleep Mode Current (VDD=5V) 1A 15A
Bit 1(/DED) :
Differential Energy Detect function enable bit 0/1 Enable / disable DED function
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
63
EM78815 8-Bit Microcontroller
7.10 Call Waiting Function Description
TIP
DATA
RING
FSK demodulator
/CD
GAIN CWTIP +
Filter Voltage reference
Detection block
CAS
Vdd/2
Fig.28 Call Waiting Block Diagram
Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. This way the customer can still receive important calls while engaged in a current call. The Call Waiting Decoder can detect CAS (Call-Waiting Alert Signal 2130Hz plus 2750Hz) and generate a valid signal on the data pins. The call waiting decoder is designed to support the Caller Number Deliver feature, which is offered by regional Bell Operating Companies. In a typical application, after enabling the CW circuit (by R5 Page 3 Bit 3 & Bit 4 ) this IC receives Tip and Ring signals from twisted pairs. The signals as inputs by the preamplifier, and the amplifier sends input signal to a band pass filter. Once the signal is filtered, the Detection block decodes the information and sends it to RE Page 2 Bit 7. The output data is made available at RE CAS bit. The data is CAS signals. The CAS is normal high. When this IC detects a 2130Hz and a 2750Hz frequency, the CAS pin goes to low.
64 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
7.11 Differential Energy Detector (DED)
EGIN1 EGIN2
DED
DEDD
DEDPWR DEDTHD
EGCLK
Fig.29 DED Block Diagram
The Differential Energy Detector is differential input level and zero crossing detector named as DED. It can detect any incoming AC signal above its threshold level and outputs a corresponding zero-crossing frequency pulse. For this energy detector, user can set its minimum detection threshold level at -35dBm or -45dBm through the DEDTHD bit. All the minimum detection value can be achieved under an input capacitor of more than 4700 pF and input resistor of 100 k. The energy detector can be power-controlled by IOCE Page 1 Bit 1 (DEDPWR). Register bits of the Energy Detector :
Register Bits RF Page 0 Bit 3 (DED) IOCE Page 1 Bit 7 (DEDD) IOCE Page 1 Bit 5 (EDGE) IOCE Page 1 Bit 4 (WUEDD) IOCE Page 1 Bit 6 (DED) IOCE Page 1 Bit 0 (DEDTHD) IOCE Page 1 Bit 1 (DEDPWR) IOCE Page 1 Bit 2 (DEDCLK) Descriptions DED : Interrupt flag of DED output data DEDD : Output data of DED EDGE : edge control of DED output data 1/0 Falling edge trig. / Rising edge and Falling edge trig. WUEDD : Wake-up control of DED output data 1/0 enable/disable DED : Interrupt mask of DED output data 1/0 enable/disable interrupt of DED output data DEDTHD : Minimum detection threshold of DED 0/1 -45dBm/-30dBm DEDPWR : Power control of DED 0/1 power off/power on DEDCLK : operating clock of DED 0 : low frequency clock 1 : high frequency clock
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
65
EM78815 8-Bit Microcontroller
8
Absolute Maximum Ratings
Rating Symbol VDD Vin Ta Min. -0.3 VDD-0.5 0 VDD 25 Typ. Max. 6 VDD+0.5 70 Unit V V C
DC Supply Voltage Input Voltage Operating Temperature Range
9
DC Electrical Characteristic
(Operation current consumption for Analog circuit)
Parameter Symbol I_FSK I_CW I_DR I_DTMF I_DA I_CMP Condition VDD=3V, CID power on VDD=5V, CID power on VDD=3V, DTMFr power on VDD=3V, DTMF power on VDD=3V, CDA power on VDD=5V, PT power on Min. - - - - - - Typ. 1.5 1.5 1.5 0.5 1.5 0.1 Max. 2.5 2.5 2.5 0.8 4 - Unit mA mA mA mA mA mA
Operation current for FSK Operation current for CW Operation current for DTMF Receiver Operation current for Tone generator Operation current for Current DA Operation current for Comparator
(Ta=0C ~ 70C, VDD=3V 5%, VSS=0V)
Parameter Input Leakage Current for input pins Input Leakage Current for bidirectional pins Input High Voltage Input Low Voltage Input high threshold Voltage Input low threshold Voltage Clock Input High Voltage Clock Input Low Voltage Symbol IIL1 IIL2 VIH VIL VIHT VILT VIHX VILX - VOL1 - IPH ISB1 Condition VIN = VDD, VSS VIN = VDD, VSS - - /RESET, TCC, RDET1 /RESET, TCC, RDET1 OSCI OSCI Min. - - 2.0 - 2.0 - 1.8 - 2.0 2.0 - - - - Typ. - - - - - - - - 2.4 2.4 - - -10 1 Max. 1 1 - 0.8 - 0.8 - 1.2 - - 0.4 0.4 -15 4 Unit A A V V V V V V V V V V A A
Output High Voltage (Ports 8, 9, B, C, D) VOH1 IOH = -6mA Output High Voltage (Ports 6, 7) Output Low Voltage (Ports 8, 9, B, C, D) Output Low Voltage (Port 6, 7) Pull-high current Power-down current (Sleep mode) IOH = -10.0mA IOL = 6mA IOL = 10.0mA Pull-high active input pin at VSS All input and I/O pins at VDD, output pin floating, WDT disabled
66 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Parameter Low clock current (Green mode)
Symbol ISB2
Condition All input and I/O pins at VDD, CLK=32.768kHz, WDT disabled, Output pin floating All analog circuit disabled /Reset=High, PLL enable CLK=3.579MHz, Output pin floating, All analog circuits disabled -
Min. -
Typ. 30
Max. 40
Unit A
Operating supply current (Normal mode) Tone generator reference voltage
ICC Vref2
2 0.5
3 0.7
mA VDD
Differential Energy Detector (DED), (Ta=25C, VDD=3.0V 5%, VSS=0V)
Symbol EGIN1 EGIN2 Parameter Operating current for SED Operating current for SED Condition SEDCLK bit = 0 SEDCLK bit = 0 Min. Typ. 20 20 Max. 25 25 Unit A A
10 AC Electrical Characteristic
CPU Instruction Timing (Ta=25C, VDD=3V, VSS=0V)
Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period
Note: N = selected prescaler ratio
Symbol Dclk Tins Tdrh Ttcc Twdt
Condition
Min. 45
Typ. 50 60 550 16
Max. 55
Unit % us ns ms ns
32.768kHz 3.579MHz
Note 1 Ta = 25C
(Tins+20)/N 16
ms
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
67
EM78815 8-Bit Microcontroller FSK AC Characteristic (Vdd = 3V, Ta = +25C)
Characteristic FSK Sensitivity Low Level Sensitivity Tip & Ring @SNR 20dB High Level Sensitivity Tip & Ring @SNR 20dB Signal Reject FSK Twist Positive Twist (High Level) Positive Twist (Low Level) Negative Twist (High Level) Negative Twist (Low Level) +10 +10 -6 -6 - - - - - - - - dB dB dB dB -40 - - -48 0 -51 - - - dBm dBm dBm Min. Typ. Max. Unit
CW AC Characteristic (Vdd=3V,Ta=+25C)
Characteristic CW Sensitivity Sensitivity @SNR 20dB USA & Europe Mode Low Tone Frequency 2130Hz High Tone Frequency 2750Hz Chinese Call Waiting Mode Low Tone Frequency 2130Hz High Tone Frequency 2750Hz Chinese SMS Mode Low Tone Frequency 2130Hz High Tone Frequency 2750Hz CW Twist Twist 7 - - dB - - 5.5 5.5 - - % % - - 2.0 2.0 - - % % - - 1.2 1.2 - - % % - -38 - dBm Min. Typ. Max. Unit
DTMF (DTMF Receiver) AC Characteristic (Vdd = 3V, Ta = +25C)
Characteristic DTMF Receiver Low Level Signal Sensitivity High Level Signal Sensitivity Low Tone Frequency High Tone Frequency DTMF Receiver Noise Endurance Signal-to-noise Ratio 15 - - dB - - - - -36 0 2 2 - - - - dBm dBm % % Min. Typ. Max. Unit
68 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
Tone Generators for AC Characteristic (Vdd = 3V, Ta = +25C)
Characteristic Tone 1/Tone 2 signal strength (root mean square voltage) Tone 1 signal strength V1rms *1 Tone 2 signal strength V2rms Tone Twist (Tone 1 - Tone 2) twist Tone frequency deviation Frequency deviation
1
Min. 130
Typ. 155 1.259V1rms
Max. 180
Unit V V
*1
- -
-2 -
- 1
dB %
Note * : V1rms and V2rms has 2dB difference. It means 20log (V2rms/V1rms) = 20log1.259 = 2 (dB)
DED AC Characteristic (Vdd = +3.0V, Ta = + 25C)
Characteristic Input sensitivity TIP and RING for DED, DEDTHD bit=0 Input sensitivity TIP and RING for DED, DEDTHD bit=1 Min. - - Typ. -45 -35 Max. - - Unit dBm dBm
Timing characteristic (Vdd = 3V, Ta=+25C)
Description Oscillator Timing Characteristic OSC start up 32.768kHz 3.579MHz PLL Symbol Tosc - Min. - - 3 - - - - - - - - - - - - - 560 250 250 250 - - Typ. - - - 18 10 10 15 - 80 42 26 Max. 1500 10 - - 14 20 20 4 - - - - - - - - - - - - 30 30 Unit ms us uS mS ms ns ms ms ms ms ms - ms mS us ms ns - ns ns ns ns 69
Timing characteristic of reset Minimum width of reset low pulse Trst Delay between reset and program start Tdrs FSK Timing Characteristic Carrier detect low Tcdl Carrier detect low to data valid Tcdv Power up to FSK(setup time) Tsup End of FSK to Carrier Detect high Tcdh CW Timing Characteristic CAS input signal length Tcasi (2130, 2750 Hz @ -20dBm) Call waiting data detect delay time Tcwd Call waiting data release time Tcwr DTMF Receiver Timing Characteristic Tone Present Detection Time Tdp The guard-times for tone-present Tgtp (C=0.1F, R=300K) The guard-times for tone-absent Tgta (C=0.1F, R=300K) Propagation Delay (St to Q) Tpq Tone Absent Detection Time Tda SPI Timing Characteristic (CPU Clock 3.58MHz and Fsco = 3.58MHz /2) /SS set-up time Tcss /SS hold time Tcsh SCLK high time Thi SCLK low time Tlo SCLK rising time Tr SCLK falling time Tf Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
*1
30 30 8
*2
- - - - 15 15
EM78815 8-Bit Microcontroller
Description SDI set-up time to the reading edge of SCLK SDI hold time to the reading edge of SCLK SDO disable time
Note * : Controlled by software *2 : Controlled by RC circuit
1
Symbol Tisu Tihd Tdis
Min. 25 25 -
Typ. - - -
Max. - - 560
Unit ns ns ns
Data ROM access timing characteristic
Symbol Tdiea Tdiei Tiew Tdca Tacc Tcds Tcdh Tdca-1 Description Delay from Phase 3 end to INSEND active Delay from Phase 4 end to INSEND inactive INSEND pulse width Delay from Phase 4 end to CA Bus valid ROM data access time ROM data setup time ROM data hold time Delay time of CA-1 C1=100pF C1=100pF 100 20 20 30 Condition Cl=100pF Cl=100pF 30 30 Min. Typ. Max. 30 30 Unit ns ns ns ns ns ns ns ns
70 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
11 Timing Diagrams
ins
Fig. 30 AC Timing
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
71
EM78815 8-Bit Microcontroller
FIRST RING 2 SECONDS TIP/RING
0.5 SEC
0.5 SEC
SECOND RING 2SECONDS
/ TRIG Tcdl /CD Tdoc DATA (internal clock) Tsup /358E DATA Tcdh
3.579 M Hz
Fig. 31 FSK Timing Diagram
plug in on hook Events Normal In use
CAS Tcasi
Tcwd CAS Tcwr
CWPWR
Power-off
Power-on
Fig. 32 Call Waiting Timing Diagram
72 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
TONE Tdp 5~20mS by S/W Tgtp 30mS Typ. ST/GT
TONE Tgta 30mS Typ.
EST
Vtst 1/2 VDD Tpq 8 uS Typ.
Q4..Q1
STD
LINE_ENG
Fig. 33 DTMF Receiver Timing Diagram
VDD
OSC
Power on reset
Toscs
Trst
/RESET
Tdrs Tdrs
Program Active
Fig. 34 Relationship between OSC Stable And Reset Time
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
73
EM78815 8-Bit Microcontroller
12 Application Circuit
LCD pannel 65x264 pixels
COMMON
SEGMENT
COMMON
FR CL /DOF V0 V1 V2 V3 V4
SEGMENT
FR CL /DOF LCD driver V0 EM9L8580(master) V1 V2 ( support max 65x132 pixels) V3 V4 P/S M/S D0..D7 /RES CLK A0 /RD /WR /CS1
LCD driver EM9L8580(slave) ( support max 65x132 pixels)
/RD /WR /CS1 /RES P/S M/S VDD
D0..D7 CLK A0
VDD
8
XOUT
Reset PB7~PB0 VDD,AVDD VDD XIN 27p 27p 0.1u 32.768k XOUT PLLC AVSS,GND EGIN1 4700p 47K EGIN2 47K TIP 4700p 47K RING 47K CWGS CWIN
PC5
PC4
TIP LINE RING 4700p
EM 78815
PC7
PC6
PC3 PORT80 PORT95 PORT96 PORT97 P70 STGT EST
Key matrix
P71
P72 P73 VDD
4700p
E x pandi ng m em or y i nter f ace
EX T ERN A L M em or y
47p
150K
39K
4700p
L i ne I nterf ace
Speech N etw ork
Fig. 35 External Multi-chip LCD Driver Application Circuit
74 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
EM78815 8-Bit Microcontroller
APPENDIX
A
Application Note
1. In targeting interrupt and program run to address 0x0008, ACC, R3 (Status), R5 (Program Page) and R4 (6, 7) will be automatically saved and R3 (6, 7) R register page will be set to Page 0, and reload after the instruction "RETI". 2. 0V reference voltage will power down when both RD Page 2 Bit 7 (DAREF) and RA Page 2 Bit 7 (CMPEN) are cleared to 0. 3. Before using Keytone function, set Port 76 as output type. 4. For accessing data ROM, EM78P815 (OTP) can work at 10.74MHz, but note that only ROM type EM78815 can work at 5.3MHz. 5. While switching the main clock (regardless of high freq to low freq or vice versa), adding 6 instructions delay (NOP) is required. 6. Do not switch the MCU operation mode from normal mode to sleep mode directly. Before going into sleep mode, switch the MCU to green mode first. 7. Always keep RA Page 0 Bit 7 = 0, otherwise, unexpected error will occur.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
75
EM78815 8-Bit Microcontroller
76 *
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)

▲Up To Search▲

Price & Availability of EM78815

	To Download EM78815 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .